AUSTIN, TEXAS — Silicon Laboratories has announced the expansion of its broad portfolio of reconfigurable, frequency-agile precision clocks to include a single input, single output jitter-attenuating clock multiplier IC. Designated the Si5319 Any-Rate Precision Clock, it is capable of generating any output frequency from either a crystal or reference clock input with 0.3 picoseconds jitter generation.
The Si5319 supports a free-run mode of operation, enabling the device to be used as a frequency flexible, low jitter clock generator when supplied a crystal input. It is ideal for providing clock synthesis, clock multiplication and jitter attenuation in high performance timing applications such as SONET/SDH/OTN line cards, WDM line cards, wireless basestations, synchronous Ethernet routers, test and measurement equipment and broadcast video.
The Si5319 is based on Silicon Labs' patented, third generation DSPLL' technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated phase-locked loop (PLL) solution that eliminates the need for external voltage-controlled crystal oscillator (VCXO) and loop filter components. The chip provides superior frequency flexibility compared to competing IC and quartz-crystal based devices given its ability to accept any frequency from 2 kHz to 710 MHz and generate any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz.
This precision clock provides a highly integrated, cost-effective jitter attenuation solution for next-generation multi-rate line cards that must support a broad array of client-side and line-side interfaces, including SONET/SDH, 1G/10G Ethernet, Fiber Channel, OTN and HD-SDI. The timing architecture is dramatically simplified because a single Si5319 can generate all required reference frequencies with extremely low jitter, eliminating the need for multiple high frequency VCXOs.
A free-run mode of operation greatly simplifies clock startup issues in high performance applications. In these systems, customers typically use a high frequency crystal oscillator (XO) to generate an initial reference clock for the transceiver driving the high speed fiber optic link. After initial startup, the system requires a reference clock that is synchronized to another clock in the system not available at startup. Traditional approaches require external multiplexer (mux) circuitry to switch between the high frequency XO and the long-term reference clock.
The Si5319 solves this problem by locking to an inexpensive crystal input at startup and switching to an active input clock when available. No external mux components are required and the clock switchover is seamless, minimizing output clock phase transients that would otherwise generate bit-errors in the high speed fiber optic interface.
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