Weybridge, UK — Analog Devices has introduced 18 power-efficient analog-to-digital converters (ADC) with resolutions ranging from 10 to 16 bits. Designed for power-sensitive communications, industrial, portable-electronics and instrumentation equipment, the ADCs reduce power consumption by as much as 60 percent compared to many competing devices, while maintaining best-in-class noise performance and dynamic range. Improved power efficiency, for example, enables wireless basestations to operate more cost effectively with better system reliability.
The flagship converter in this series, the AD9268, claims to be the industry's first 125-MSPS (megasamples per second) 16-bit, dual-channel ADC and consumes 376 mW per channel — 60 percent less power per channel than competing devices. The ADC's integration and energy savings allow system engineers to increase channel counts without increasing a product's board area or power consumption, enabling higher call volume in cellular base stations, for example, or improved image resolution in medical magnetic-resonance imaging (MRI) equipment. In handheld and other power-sensitive applications, the low-power ADCs likewise enable improved system performance while extending battery life in hand-held devices, such as portable spectrum analyzers.
The AD9268 dual-channel, 16-bit ADC is available in speed grades of 80, 105, and 125 MSPS. The 125-MSPS option achieves 78 dB SNR (signal-to-noise ratio) and 90 dB SFDR (spurious-free dynamic range) to 70 MHz analog input frequency, while consuming 376 mW per channel.
Available in a Pb-Free, 9 mm x 9 mm chip-scale package, the AD9268 is pin-compatible with the company's other low-power ADCs. This speeds product upgrades, simplifies new-product engineering debug, and improves time-to-market by reducing the number of separate ADC pin-outs that manufacturers must support.
Another converter in the series, the AD9251 is a dual-channel 14-bit ADC and is available in the same 64-lead LFCSP pin-compatible footprint and is offered in speed grades of 20, 40, 65, and 80 MSPS. With 73.5 dB SNR and 85 dB SFDR to 70 MHz analog input frequency, the AD9251 dissipates only 86 mW per channel at 80MSPS, improving power efficiency by more than 50 percent over competing 14-bit ADCs.
All of the low-power dual ADCs operate from a single 1.8-V analog power supply and feature a high-performance sample-and-hold circuit and on-chip voltage reference. The AD9251 family offers a separate driver supply to accommodate 1.8-V or 3.3-V CMOS logic outputs, while the AD9268 family offers 1.8-V LVDS or CMOS outputs.
The ADC cores use a multi-stage, differential pipelined architecture with integrated output error-correction logic. They also contain features designed to maximize flexibility and minimize system cost, including programmable clock and data alignment and programmable digital test-pattern generation. The available digital test patterns include built-in, deterministic and pseudo-random patterns, as well as definable test patterns that users can enter via the serial port interface (SPI).
Further, the company's low-power ADCs are compatible with their dual-channel VGA (variable gain amplifiers), including the AD8372 programmable dual VGA and AD8376 IF dual VGA as well as the ADL5561 differential RF/IF amplifier and ADL5562 differential RF/IF amplifier. Recommended clock generators include the AD9520-0 and AD9522-0.
Further information and data sheets are available.