Success in the digital-signal-processor communications market comes down to a keen understanding of applications and system-level solutions. Designers need low-cost, high-performance DSPs designed for their specific markets. In the wireless communications market, the processing needs of the algorithms are well known, but cost, performance, size and power consumption place multidimensional constraints on system design.
Design issues for basestation designers boil down to maximizing the number of channels processed per printed circuit board while keeping the size and power consumption of that board compatible with space and cooling constraints. DSP silicon destined for next-generation wireless applications must meet criteria that include focused architecture and processing expertise, decreased size and power consumption, improved cost and shortened time-to-market.
But the real key to optimizing performance is to ensure that the architecture and its instruction set are matched to the needs of the application. DSP core designers must balance instruction width (code size) with the number of operation codes available to implement an instruction set. No one architecture is best at all applications; just comparing Mips provided by architecture A to Mips provided by architecture B is no guarantee of selecting an optimum DSP.
Likewise, many wireless applications lend themselves to multiple processor implementations, so silicon with twin processing cores that can accommodate the cost and power constraints would be a big advantage over single-core engines. Fast access to memory is also an architecture concern. On-chip direct-memory-access (DMA) controllers represent a big advantage here, and such considerations even extend to process-technology developments. Those optimized for communications would be designed around high-density SRAM and DRAM, as well as mixed-signal capabilities (BiCMOS).
In basestations, lower power consumption allows denser packing of devices, eliminates cooling systems, cuts power-supply requirements and improves system reliability. For many DSP designs, chip power consumption is driven by the on-chip memory and the native instruction set, which determines the number of gates needed. The trade-offs are complex. More gates and therefore more power consumption mean increased number crunching per cycle. An alternative is to design for higher performance through higher clock speeds, but that raises power consumption.
Meanwhile, shrinking design geometries and refinements in DSP architectures make the core area a small fraction of overall silicon area. At the same time, the trend is to incorporate the memory needed to support a given application on-board to maximize performance while minimizing board area, power and cost. Therefore a DSP's die size, and thus its cost, is dominated by the memory complement. Efficient architectures enable programs with minimal memory requirements.
In many applications, system designers need DSP products that are supported by comprehensive tools for fast prototyping, efficient code generation, rapid and smooth system integration, and intelligent testing and debugging capabilities. In wireless applications the rule of thumb is that while C compiler output is adequate for the prototype design phase, overhead inefficiency in production systems cannot be tolerated. Hand-optimized DSP assembly code is still the workhorse methodology for implementing the compute-intensive and performance-sensitive algorithmic inner loops found in wireless systems. Controller code may be left in C.
For OEMs with extensive libraries of DSP applications code, compatibility between DSP generations can be a crucial design consideration. Compilers and translators can minimize code porting efforts but optimization of code space and performance will highlight the tradeoff between software compatibility and time-to-market. Intelligent reuse of debugged algorithms on new silicon is still a smart way to protect an OEM's investment.
Lucent's DSP1695 for Internet equipment nearly triples the number of voice and data calls that can be processed by Internet service providers and telephone service providers. The chip integrates four DSP core subsystems and is for use in remote access concentrators and servers, central-office switching systems and other network access equipment. The Lucent DSP16410. also for basestations, includes two DSP16000 cores. That translates into 29 Enhanced Full Rate speech coders on one chip-and lower basestation costs.