Even with the help of highly specialized tools that cover all of the facets of a design flow, the critical act of designing at the transistor level is still performed with a rough balance of designer experience-which has no substitute-trial and error, and analog simulators. Analog simulators are as good as the information provided to them, so the heuristic methodology used in the design process can be identified as the root of much of the time and frustration experienced in a design cycle.
The process of "tweaking" the parameters within a circuit topology to get the last bit of performance or shave off another 10 percent or so of power consumption is usually one that's done by hand, requiring several iterations. The designer must take great care to understand the sensitivity of the component parameters that are to be varied against the performance goals and the positive or negative role each parameter must take to hit that target.
As circuit device count and/or crucial design specifications grow in number, the hope of ever finding optimum solutions diminishes rapidly. That can lead to suboptimal circuit behavior, which increases the possibility of an expensive ($250k U.S. or more) design turn. That will affect time-to-market for the chip as well as the system or end product for which it is designed-all of which have a limited time to maximize revenue.
The design cycle's efficiency can be significantly improved by reducing the amount of trial and error spent on design trade-offs. Here, the circuit optimizer can be a valuable tool in the design-trade-off process.
Essentially, a circuit optimizer is a tool that is designed to alter a circuit's parameter to match a given performance target. Mathematically, a circuit topology is expressed in terms of equations and matrices within an analog simulator; optimizers will iterate those series of equations to achieve the best overall match of circuit values vs. circuit performance. The basic use model of an optimizer is fairly straightforward.
First, the user defines, within a GUI, the circuit parameters in the schematic to be varied, along with the maximum and minimum values for each parameter. Then the designer enters the performance targets to be minimized or maximized-whether they're classical metrics such as bandwidth, noise, output current or user-definable quantities. At this point the user may also enter an acceptable range for each goal- basically defining "how good is good enough" for the tool.
Next, the initial simulation is launched, with the help of an associated analog simulator. The tool will use that to evaluate the sensitivity of each variable vs. the performance goals. Further simulations will be launched automatically until the preset goals are achieved or the ranges of variable values are exhausted. The progress of each design variable that is changed, as well as progress toward the performance targets, is monitored in real-time.
Many circuits fail to meet their intended performance goals. Individual components may contribute, making a satisfactory back-of-the-envelope solution less likely. Proper use of a circuit optimizer can help. Used in a precise fashion, these tools can find the simple circuit solutions faster than trial-and-error methods can. They also can determine those complex design points (with multiple inputs and multiple design targets) that were previously intractable.
The developer may use optimization to address a wide range of design tasks, from retargeting or resizing an existing transistor-level design for a new semiconductor process, to balancing a PLL's loop filter jitter vs. response, to determining RF amplifier load-pull contours.
For example, a designer building a low-noise amplifier may be required to maximize bandwidth while minimizing noise. When varying the input-stage device sizes and resistances, the problem becomes nontrivial for hand calculation, since those variables will conflict with the overall goal. However, the designer can achieve the optimum design by using a circuit optimizer.
For a commercial optimizer to be embraced by the design community at large, it must be easy to use, flexible and provide accurate solutions to many classes of circuit problems. Increasing the efficiency of the custom design flow should include the physical design space as well as simulation. The two should work in concert, but in conventional custom flows there's no direct link. The growing popularity of the advanced Automated Custom Physical Design flow, which uses parameterized physical cells, unveils a useful avenue for circuit optimization.
Linking transistors and code
Top-down analog design has been made possible by the advent of such analog hardware-description languages as Verilog-A or VHDL-AMS. They allow the designer to envision and simulate a design at a higher level of abstraction to validate the overall chip functionality before designing the constituents at the transistor level. Customers insist that the output of a block written in an analog HDL must match the output of its corresponding transistor-level design. Optimization can take a leading role by serving as a link between transistors and code.
For example, when the output of a circuit designed in Verilog-A is used as a target, a transistor-level circuit's component values may then be optimized to fit this "ideal" behavior closely. The reverse case may be performed as well, optimizing analog HDL code to fit a real design's behavior. The code would be ready for use in simulation for its intended design, or as IP for derivative projects. While that is not the equivalent of digital synthesis, it will provide a methodology in which code and transistors will have a reasonable correlation.