Digital signal processing is a technology more than a market. But as such, it is the enabler for the most popular application of this decade, and possibly the next: communications. DSP shapes the phase and frequency of 2,400-kHz carriers to effect 56-kbit/second analog modems. It puts 255 discrete multitones on the telephone over standard phone lines, to effect a 1.5-, 6- or 8-Mbit/s asymmetric digital subscriber line (ADSL). It enables GSM, TDMA and CDMA modulation patterns for today's cellular telephones and will enable two-way voice, pictures and data on future cellular handsets. And it converts digitized voice into TCP/IP packets for transmission on the Internet.
Thus, it will be communi-cations applications-and the means of implementing them-that will take center stage when the annual DSP World Conference and Exhibition opens in Orlando, Fla., this week.
Participants in the prestigious Industry Technology Forum, the one-hour panel that precedes the formal opening of the show, represent a broad cross-section of the DSP industry. Applicants to the forum-manufacturers with new products to exhibit-include developers of general-purpose digital signal processors and cores, application-specific cores, DSP compilers and software development tools, programmable-logic implementations of DSP functions and applications, single-board computers and entire box-level DSP systems. But apart from one startling new DSP architecture, it will be DSP applications, especially in voice and datacom, that will dominate this year's forum.
The hardware marvel in question is the SP-5 DSP core from 3DSP (Irvine, Calif.), which represents a significant departure from the architectures of other emerging high-performance DSP cores, the vast majority of which embrace-or at least flirt with-very long instruction word (VLIW) architectures. The best-known devices using VLIW include Texas Instruments Inc.'s TMS320C6000 series and the StarCore SC140, developed by a joint venture of Lucent Technologies and Motorola Semiconductor. The Infineon Carmel and Philips' R.E.A.L. DSPs approach VLIW in a customizable long instruction word (CLIW). But while all of those devices perform many operations in each clock tick, they are highly dependent on the scheduling (and register selection) of a tuned C compiler.
The 3DSP core radically departs from that model by using single instruction/multiple data (SIMD) execution. Its developers, June Jiang and Kan Lu, were looking to strike a balance among high performance, low cost, low power consumption and programming ease.
The device is a superscalar pipeline with a memory-to-register file architecture. It can do two SIMD instructions at once with a totally variable data format, yielding a compact code density. Jiang assumes users will program the core by hand, with a C-like assembler, freeing themselves of the need to track register allocations and memory addresses.
Other DSP architectures submitted for inclusion in the Industry Technology Forum (ITF)-like the Palm DSP core from the DSP Group (Tel Aviv)-follow the broader trend in general-purpose DSPs toward parallelizing resources. Though not a VLIW or CLIW machine, the Palm core has two multiply-accumulate units and uses extensive instruction-level parallelism. It performs fixed point in a choice of word widths: 16, 20 or 24 bits. Instruction width can vary from 16 to 32 bits. Code-compatible with other popular DSP Group cores, such as the Oak, the Palm is targeted at cell phone handsets, digital subscriber lines, pooled modems and Internet gateways. Yet it is still a general-purpose DSP that can be programmed to serve other applications.
3DSP's June Jiang shows the SP5 core, an unconventional architecture based on SIMD execution, used in a digital camera design
Some cores selected for the ITF focus on specific applications. Cores from Massana Inc. (Campbell, Calif.) target such comms applications as voice-over-Internet Protocol and ADSL. The company's Filu-DMT is meant to supplement the Pentium and other PC processors in decoding splitterless ADSL-or G.Lite-signals. The Filu-DMT works with the Pentium host in deciphering the discrete-multitone (DMT) signals that are used to symbolize data on home phone lines. Users can develop their G.Lite applications in C and use a Massana application programming interface to invoke preprogrammed G.Lite functions from the Filu-DMT core, which is described as a dual multiply-accumulate architecture with dual adders and barrel shifters. Intended for complex number arithmetic, the core has a 20-bit internal data path, which will provide a number-processing capability close to that of a floating-point unit, the company said.
Repeatedly, manufacturers of programmable logic have shown that certain DSP functions will execute faster on a hardwired FPGA than on a general-purpose DSP. Certain types of math operations, particularly convolutional encoding and decoding-the insertion of error correction codes in the communications data streams, or in data storage applications-are easily implemented in programmable-logic devices.
Altera Corp. (San Jose, Calif.), provides a library of DSP functions for its users-Reed-Solomon and Viterbi decoders, DES data encryption devices, FFT processors and adaptive equalizers among them. The company recently purchased a DSP developer, Hammercores (Maple, Ont.), to ensure an uninterrupted flow of intellectual property.
At the ITF, Altera will demonstrate its implementation of voice-over-IP. In an FPGA, the device is a multichannel echo canceler using an adaptive FIR filter. It processes micro-Law and A-Law encoded voice data through 768 channels and snip "tail lengths" up to 150 milliseconds. It can reduce the cost of echo cancellation in voice-over-IP systems by as much as tenfold compared with general-purpose DSP implementations, said Martin Langhammer, founder of Hammercores and Altera's chief DSP scientist.
The need for multiprocessor support will be addressed at the ITF by Honeywell Space Systems (Toronto) and Sky Computers (Chelmsford, Mass). Honeywell's Systems and Applications Genesis Environment (Sage) provides automated partitioning and mapping for distributed application software. Sage, according to its promoters, can capture the knowledge of an underlying processor and its run-time requirements, and can automatically partition a software application among connected processors.
The first release of Sage supports Alacron Sharc DSP boards and was hosted on Windows 95, 98 and NT. The company is developing extractors for Force Computer's UltraSparc-based boards and Blue Wave Systems' TMS320 DSP boards. Also planned is support for CSPI's Quad PowerPC boards.
Sky Computers will use the DSP World event to demonstrate its Merlin multiprocessor system, also based on the PowerPC. The Merlin puts daughtercards with four Motorola MPC7400 processors on a 6U VMEbus motherboard that will process up to 10.6 Gflops (672 Gflops in a single VME chassis). Processors are linked by a SKYchannel 320-Mbyte/s packet bus.
Support for multiprocessor systems is also being developed by BOPS Inc. (Palo Alto, Calif.). At DSP World, BOPS will demonstrate a compiler for the Matlab high-level simulation tool from The MathWorks (Natick, Mass). The compiler is said to convert Matlab's M code into assembly code for parallel processors. It will generate a VLIW and map it across parallel execution resources.