Broadband digital communication systems are continually pushing the data bandwidth closer to the fundamental channel capacity limit. Advances in digital-signal-processor algorithms and their implementations in deep submicron CMOS processes have made this possible. However, this creates a huge challenge in the design of the broadband high-precision analog front end that must be integrated with the DSP.
A recent example is the device that is based on the emerging IEEE802.3ab-based Gbit/second Ethernet data-networking physical layer (channel) for use with standard unshielded twisted-pair CAT5 cable. While current generations of Fast Ethernet devices use one pair of the cable solely for transmitting and another pair just for receiving, the future-generation Gigabit IEEE802.3ab device uses each pair of the cable for transmitting and receiving data simultaneously. To compound the problem, that device utilizes five-level data encoding, reducing the receiver signal-to-noise (SNR) ratio by 6 dB from that of the Fast Ethernet device. Additional SNR degradation is unavoidable because of crosstalk caused by signal interference from adjacent pairs of cable in the same bundle. Finally, while incorrect cable installation or the use of lower-quality, low-cost CAT5 cable had been known to cause intermittent errors in traditional non-DSP-based Fast Ethernet systems, it is expected that these same wiring systems may now cause huge problems in the deployment of Gigabit Ethernet networks.
The solution is not to replace the existing CAT5 wiring with CAT5e or CAT6 cable, but instead to use even more advanced DSP algorithms borrowed from other broadband digital communication systems and partial-response maximum-likelihood (PRML) read-channel devices. To distinguish the weak received signal from the strong transmitted signal found in long cable installations, the IEEE802.3ab employs adaptive digital-echo and near-end crosstalk cancellation technologies.
To recoup the 6-dB loss of SNR from the increase in the coding density, a complex decision feedback equalizer Viterbi detection technique is used. Because these complex digital signal-processing algorithms must run in real time, it is estimated that between 1 million and 2 million gates of hard-wired custom parallel DSP engine is needed. Therefore, to achieve low power and small die size, sub-quarter-micron CMOS processes should be considered for implementation of this device. By running the digital circuit at low voltages, hundreds of billions or even trillions of operations per second can be performed in the custom DSP while dissipating extremely low power. However, while the scaling down of CMOS processes has benefited the digital circuitry, it has created a huge challenge in the design of precision analog circuits.
It is widely known that as CMOS devices scale down in size, transistor properties such as drain-to-source output impedance, device-to-device matching and power supply voltage tolerance are drastically affected. The solutions to these problems must be obtained from a combination of clever analog circuit topologies and to fundamentally do the unthinkable-move as many analog functions into the digital domain as possible.
Consider the A/D converter needed for the IEEE802.3ab device. Based on extensive simulations by the IEEE802.3ab standards committee, it has been found that a minimum of 7 bits of A/D converter resolution is needed to achieve an acceptable overall error rate performance at 100 m of CAT5 cable. One of the most suitable converter topologies to achieve a high conversion rate is a fully parallel flash A/D converter. However, a 7-bit flash A/D converter requires 127 high-speed, low-power, low-offset voltage comparators-a large number. Unfortunately, these requirements are not naturally achievable all at the same time. Commonly used techniques to reduce comparators' offset voltages such as auto zero techniques do not work well for this application as they effectively require the comparators to work with only half of the already short conversion time (less than 4 ns from the original 8 ns). Furthermore, an even higher resolution A/D converter may be needed to support more than 100 m of coverage, increasing the challenge in designing the A/D converter.
A proven technique that was originally developed for use in Marvell's PRML read channel A/D converter is the digital self-calibration technique for calibrating the offset voltages of the individual comparators. This technique makes it possible to employ small transistors in the comparators to achieve low power dissipation and small die size. As MOS cut-off bandwidth, fT, is inversely proportional to the square of the channel length, short channel devices can additionally be used to achieve higher bandwidth and conversion speed at a given power dissipation. Digital calibration effectively moves the complexity of the flash A/D converter design into digital domain, making the converter performance less dependent on process variations.
Another nontrivial analog building block of the Gigabit 802.3ab device is the output transmitter D/A converter. Because of the echo cancellation requirement for a full duplex communication, the linearity of the transmitter D/A converter must be at least equal to that of the receiver. At the same time, the IEEE802.3ab requires that the transmitter D/A converter must meet stringent rise and fall time requirements. However, traditional Fast Ethernet designs using R-C time constant to control the D/A converter slew rate are not portable nor are they scalable across different processes. A better solution to this problem is to oversample the transmitter D/A converter's update rate by adding a simple interpolating digital filter. In general, it is easier to run the converter at a higher clock rate than to control the precision of the slew rate of the converter. By running the converter at a much higher sample rate than otherwise needed, a simple non-precision single-pole filter of high frequency is sufficient to guarantee the slew rate specification of the D/A converter.
Echo cancellation in Gigabit IEEE802.3ab designs relies on the fact that both transmit and receive signals are clocked at exactly the same frequency. A physical layer device called the master sets the sampling clock frequency. At the other end, the slave physical layer device must then precisely recover the master physical layer sampling clock. While it is obvious that short-term jitter is important in achieving high SNR, it is not so obvious in this application that a very low long-term jitter is just as important. That is because the adaptive echo canceler would not be fast enough to track the long-term variations in the clock frequency without introducing large echo canceler adaptation noise.
Again, the best way to solve this problem in deep sub-quarter-micron design is to employ a phase-locked loop with as much digital control as possible. A multiple-phase PLL allows frequency acquisition simply by rotating the tap selections to recover the received clock. Additional phase resolution can be obtained by digitally interpolating between two adjacent phase choices to achieve arbitrarily small phase adjustments.
While the solutions for different analog building blocks are inherently different, they all share the same fundamental change in the way we solve analog design problems in deep sub-quarter-micron processes. Digital gates are inexpensive; traditional analog functions are expensive to build. We must integrate as much digital functionality into the analog building blocks as possible and simplify the analog designs so that the digital circuits perform most of the compensations for variations in process, temperature and supply voltages.
Using these techniques, Marvell recently introduced the M88E3080, a DSP-based Fast Ethernet device on a single chip with eight-ports (octal). It is implemented in a triple-layer metal standard 0.25-micron digital CMOS process. This device is a subset of Marvell's Gigabit IEEE802.3ab-compliant device that is in the final design stage. An extremely low jitter and linear transmitter D/A converter is produced. This unprecedented performance level is maintained across all process corners, resulting in a highly manufacturable physical layer part. Because of the higher resolution A/D converter, lower jitter PLL, high-sample-rate D/A converter and an advanced DSP algorithm implementation, it can cover up to twice the distance of standard products.
A side benefit of moving analog functions to a digital domain is that in quarter- and sub-quarter-micron regimes, more digital and less analog translates into lower overall power dissipation. The difference in power dissipation will get wider as we move to the 0.18-micron and lower geometries.