Reusable cores are a crucial component in creating system-on-chip (SoC) designs on time and efficiently. These intellectual property (IP) blocks enable SoC designers to quickly construct highly complex ICs to meet next-generation design requirements. So why hasn't reusable IP fulfilled predictions that it will sweep through the design world?
The simple reason is that not enough attention has been paid to the verification and testability of IP. To make SoC designs practical and cost effective, reusable IP cores must be verifiable, testable and easy to rescale to a new technology without an excessive design and support effort. Consequently, the often-overlooked verification and testability criteria are the critical missing link that must be fully addressed for core design reuse to become a widespread commercial reality.
Essentially, the verification and testability of SoC designs is driven by submicron and deep-submi-cron technologies where transistor switching speeds are dominated by interconnect delay concerns. As always, the cost-time factor is also a critical concern.
When evaluating the available test and verification technologies-from traditional techniques to emerging ones like path delay, signal integrity and parametric testing-built-in self-test (BIST) solutions offer a viable way to make the reuse of IP a reality by facilitating easy testability and postproduction verification. BIST has received a lot of attention over the last couple of years as the technology of choice for SoC. Unfortunately, it is not true that every BIST solution is appropriate for digital, analog or mixed-signal IP reuse. To consider BIST an applicable solution for IP reuse, the following minimum requirements must be met:
- Digital output compatible with the standard test port.
- Reprogrammable test features (depending on the application).
- Select-based test resolution for choosing between fully functional tests for development and diagnosis or go/no-go testing for production.
- Parametric test coverage as well as functional or structural coverage.
- Minimal impact on core performances along with other characteristics dependent on the core type.
- Easy rescaling for a range of technologies and performances.
One BIST methodology that satisfies those requirements and is appropriate for IP reuse is oscillation-based BIST (Obist) implemented for voltage-controlled oscillator/phase-locked loop (VCO/PLL) circuits as well as for digital designs and A/D and D/A converters.
Basically, Obist uses the functional circuit to be tested as part of an oscillator and then evaluates the performance. A number of specific solutions appropriate for different circuits and their respective test requirements are obtained from this simple principle.
Regardless of the type of IP, Obist generates a digital output as the test answer giving easy integration to the standard test port. Each circuit (module) can support reprogrammable oscillators by changing oscillation conditions. In addition, multiple applications of Obist can be used to obtain parametric fault coverage. This is because several oscillations may be selectively affected by different circuit parameters-by design. Easy switching between oscillators gives reprogramming options depending upon the activation of different IP tests.
For example, an op amp can be caused to oscillate at two different frequencies: a low frequency to establish that it has adequate open-loop gain to overcome a large attenuation factor in the feedback loop, and at a much higher frequency to establish that it has adequate gain-bandwidth product. Or A /D converters can be thoroughly tested and characterized using repeated applications of Obist by selectively supplying pairs of codes to determine the incremental nonlinearity of the converter between those codes. Both INL and differential nonlinearity (DNL) can be extracted by extrapolation and calculated from the frequencies associated with the code pairs applied.
Another powerful characteristic of Obist is its processing flexibility. The direct output can be converted from frequency to an easily observed number. In the case of analog and mixed-signal modules, further processing of a frequency signal may be needed. This processing can be adapted to the particular test specifications like signal-to-noise ratio, total harmonic distortion and effective number of bits. For IP reuse, precise and powerful processing can be based, for example, on histograms that allow for general-purpose signal processing without the need for multiple custom analog signal-processing blocks.
Histogram methods shorten test time limitations not by acquiring and processing waveforms but by acquiring random sampling with signature generation, both of which are highly compressed signal representations. Histogram processing can be very fast and the selection of test features and resolution are easily controlled. Because that approach is so efficient, IP can be fully characterized and selected tests applied multiple times-perhaps in other SoC applications or at different stages of the design's development. Most of the specifications can be derived with histogram data, thus saving time and increasing precision.
An important area where Obist can be easily applied for the test and verification of reusable IP is in VCO and PLL IP. It is well-known in circuit theory that a circuit can be transformed into an oscillator by different techniques, perhaps closing a loop by connecting an input to an output as in the case of some filters or by using internal oscillation loops in the case of VCOs and PLLs. By using internal oscillations of a VCO module followed by frequency processing, perhaps with histograms as it is in Fluence's VCObist product, the high parametric test resolution is easily achieved. For example, it permits 0.18-micron technology on root-mean-square jitter test with 10-picosecond accuracy. The same accuracy can be achieved for rms phase jitter, delay and lock indicator. Consequently, VCObist supports precise specification testing with standard ATE capabilities and detailed testing of VCO and PLL parameters by simple digital-only test equipment.
The Obist module with histograms does not have to be integrated into a core. In reality, it can be external, on a system or on a tester. If integrated as a module on a system, the histogram technique can be used for other core testing as well. There is full compatibility and reuse of these resources. For example, the same histogram module can be used for A/D or D/A converter testing. Even digital blocks can make use of the histogram block for prototype characterization.
The VCObist IP core works by taking fast accurate measurements of the time interval between two successive low to high transitions of the input clock signal. The individual time measurements are loaded into a histogram constructed using on-chip RAM. Once the appropriate number of samples is stored in the histogram, the entire contents of the histogram RAM are transferred to a PC or a digital tester and analyzed to compute rms jitter. The same software can perform other specification computations. For example, peak-to-peak jitter is computed by multiplying the rms jitter by 6. The number of samples for histogram processing can be changed to give additional scaling and reprogrammability.
VCObist does not rely on any circuits running faster than the base design. Therefore, the upper limitation on speed is controlled by the measured circuit and not by the BIST. Before each jitter measurement, BIST circuits are continuously self-calibrating. For example, the calibration of an input VCO with a frequency of 622 MHz takes 6.7 milliseconds, jitter measurement time is 1.7 ms and the total time is 8.4 ms. Finally, area overhead is extremely small because VCObist uses a block approach for integrated histogram building and processing. Fewer than 2,000 gates are typically enough to implement VCObist.
Besides providing powerful test and verification capabilities for analog circuits, Obist techniques can also be extended to digital IP. For example, Fluence offers an implementation of Obist for digital circuits called DynBIST. It consists of creating oscillations in a digital circuit under test by first sensitizing a path with an appropriate primary input combination and then incorporating a ring oscillator to test for delay and stuck-at faults. The oscillations involve all components in the oscillating path resulting in functional and parametric testing.
The result is a dynamic test environment that permits on-delay test, rise-and-fall test and other timing-specification testing. Again, by controlling processing options, the applied tests and the result formats can be easily changed for the IP. Experiments show that it is an efficient technique for applications ranging from register high-performance tests to scan-based digital blocks to even specific nonscan blocks. With the appropriate processing software and the application of multiple oscillations, a high diagnostic resolution can be achieved.
Another powerful use of Obist for testing IP is within A/D and D/A converters. One possible implementation for an A/D converter is reconfiguring a converter into a sigma-delta-based oscillating circuit. Only a few additional circuits are needed.
Sigma-delta modulators are negative-feedback, regulation loops with an integrator, an A/D converter in the feed-forward path of the loop and a D/A converter in the feedback path. Negative-feedback regulation loops with high open-loop gain are known to be sensitive to the non-idealities of components in the feed-forward path of the loop and remain very sensitive to the characteristics of components in the feedback path of the loop.
This property of the sigma-delta loop is used to test D/A converters. The direct current-driven sigma-delta modulator forms an inherently unstable regulation loop, essentially creating an oscillation-based BIST. The advantage of this particular Obist is that it does not require any signal source and eliminates the need for precise analog measurement. Moreover, the sigma-delta approach adds a negative-feedback regulation loop that delivers high absolute accuracy and digital filtering, resulting in the higher precision of each measurement. Here again, as with other Obist techniques, this approach permits detailed performance testing, code by code or on fast production test or both.
Overall, integrated BIST, whether VCObist, DynBIST or A/D and D/A converter BIST, can greatly reduce the time-to-market and IP core-integration challenge, making the use and reuse of IP a more feasible and attractive approach for development teams looking to decrease costs and time-to-market.