Designing an intellectual property (IP) core that is robust enough to be used in many different chips becomes even more challenging in the world of ultradeep submicron-below 0.25 micron. This is because the electrical environment surrounding the IP in that submicron world can interfere with its performance and functionality. External effects such as crosstalk from neighboring signals or noise coupled through substrate can make hard IP impossible to reuse, which holds true for all IP blocks, from simple logic cells through complex microprocessor or analog cores. To protect against the hazardous effects of noise, hard IP blocks must be immunized against the major noise sources that are likely to be present where the IP is used.
The designer of a hard IP core must account for both external and internal noise effects. Internal noise comes from the circuits and wires within the core itself; external noise from other blocks and wires surrounding or crossing the core and from the substrate beneath the core.
Many different noise sources need to be analyzed when designing analog and digital IP cores, among them thermal noise, flicker noise, shot noise and substrate noise. They are a problem to analog IP designers because it represents a lower boundary on the useful amplification of a signal's magnitude. It also represents an upper boundary on an amplifier's useful gain, since it ultimately saturates the amplifier if the gain is too high.
For digital IP, noise sources that must be considered are crosstalk between internal signals; charge sharing within circuits; transistor leakage, and power supply fluctuations due to expected voltage drop on the supply lines.
Crosstalk noise-also called coupling noise-comes mainly from the capacitive coupling between two or more metal lines. Switching on neighboring nets (attackers) can inject noise onto an otherwise quiet (victim) net. The resulting noise has the form of a pulse that can alter the logic state of the victim and potentially cause a functional failure. Crosstalk can also affect the delay and slew of signals. If attacking signals are switching in the direction opposing the victim net, the transport delay from driver to receiver increases. This can lead to setup violations at downstream latches or flip-flops. If the attackers are switching in the same direction as the victim net, the transport delay decreases, potentially resulting in hold-time violations.
Charge-sharing noises occur because of charge redistribution between dynamic or weakly static nodes and internal nodes of a pull-up or pull-down stack. In dynamic logic gates, the output can be protected from charge-sharing noise by using a keeper device. However, if the keeper is omitted or is too weak, noise can cause the dynamic node to switch, resulting in a functional failure.
In ultradeep submicron, currents still flow when the transistors are nominally off. In dynamic circuits, this subthreshold leakage can pull down precharged nodes, greatly reducing their noise margin and making them very sensitive to other noise sources such as crosstalk.
Power supply noise occurs when noise appears on the on-chip power and ground lines. There are two types of such noise: dc IR drops across the chip and delta-I noise. The former is produced by variations in the dc power supply and ground levels due to IR drops in the power/ground network. The latter is produced by the simultaneous switching of off-chip drivers and internal circuits, usually synchronized with the activity of the clock. The sudden demand for current causes periodic variations in the supply and ground rails if the current must be supplied through inductance of the chip-package connection. Power supply noise greatly reduces the noise margin available to digital circuits, making them more sensitive to other noise sources such as crosstalk.
When a hard IP core is designed, it should be validated to ensure that it functions and performs as expected under worst-case noise conditions. The best way to do this for digital cores is by comprehensively analyzing noise immunity using a static noise analyzer. Static noise analysis is capable of analyzing very large cores without requiring input vectors or design rules. It can check each circuit within the IP against the worst-case noise coming from all major noise sources acting on it.
Static noise analysis can identify noise-sensitive areas within the IP core. Once the weaknesses within a core have been identified, a number of different circuit techniques can be used to improve noise immunity. For example, coupling noise can be reduced by spacing or widening wires or by inserting repeaters. To fix problems due to charge sharing or leakage the most common techniques involve adding "baby-sitting" devices to internal nodes in n-FET pull-down stacks of domino gates and half-latches to dynamic nodes.
Noise should be analyzed at the most aggressive conditions under which the IP must be functional: fast process, high temperature and high nominal voltage for each target process technology. Fast process means faster slew rates, which generate more coupling noise. High temperature means higher subthreshold currents and more leakage noise. Higher nominal voltages produce faster transitions and higher noise voltage levels relative to the threshold voltage.
Once the core has been made noise immune, an abstract noise model can be created for use by the IP integrator. This model will encapsulate how a block behaves when it is a victim of a noise and how the block will act as a noise attacker, injecting noise into its environment via its output drivers or via internal nets coupling to external wires.
As hard IP will be placed into a hostile environment, steps must be taken to model how the block will interact with its neighbors. For example, for a digital core, the worst-case effects of global routing can be accounted for by artificially shadowing the core with routing pertaining to metal layers not used within the IP block. Also, the effects of neighboring blocks can be modeled by adding routing around the edges of the core. Static noise analysis can then be performed using the output from parasitic extraction of the core and its shadow. From this analysis, the internal circuits of the core can be noise hardened to protect against noise emanating from over-the-block routing and neighboring blocks.
Of course, making an IP block noise immune typically implies trading off other design metrics such as performance or area. In some cases this may not be acceptable, and the result of noise analysis may be to enforce restrictions on how the block can be used. For example, over-the-block routing may be disallowed or a certain amount of isolation between the block and its neighbors must be enforced.
For analog IP, over-the-block routing is typically not allowed. Additionally, other special requirements arise to minimize the impact of substrate noise when the core is used for mixed-signal applications. Substrate noise is created by the switching of high-speed digital blocks residing on the same chip as the analog core.
When digital signals switch, noise is coupled into the substrate from interconnects and from the bulk terminals of the switching transistors. In addition, noise is injected into the substrate as ground bounce from the package and supply rails. Once in the substrate, noise can attack sensitive analog portions of the design, causing them to malfunction.
To manage the substrate noise problem, IP core design can resort to a number of techniques to ensure the noise immunity of their design. These include spacing the analog IP away from its digital counterparts, the use of dedicated power supplies for the core and using guard rings to shield the core. Guard rings work by absorbing noise from the substrate and deflecting it away from sensitive areas. Other techniques include using a more expensive process or package.
Substrate noise analysis allows the analog IP developer to examine the impact of substrate noise on the core. This can be performed by surrounding the analog core with digital blocks where each digital block is modeled as a simple macro model.
The effectiveness of guard rings can be studied this way. The amount of isolation required over a range of clock frequencies can also be determined. By analyzing substrate noise, a set of guidelines for the safe cost-effective usage of the analog IP can be determined.
When designing reusable hard IP for ultradeep submicron, steps must be taken to ensure the core's noise immunity. This includes reducing the core's sensitivity to noise, reducing the amount of noise it creates and developing guidelines for the core's effective use. All of these steps can be achieved through detailed noise analysis of the IP under worst-case environmental conditions.
A noise model representing the core's noise behavior for each target process should be made available to the IP integrator for noise immunity analysis of the complete system.