By bringing together the right process management, design entry, simulation and synthesis tools, engineers now can build a methodology that supports mixed schematic and language-based design for field-programmable gate arrays (FPGAs).
It's easy to see why analysts have been predicting for years that designers would migrate from schematic-based design entry methods to representations based on hardware description languages (HDLs). Using an HDL such as Verilog or VHDL offers many advantages. By allowing designers to describe their design in much the same way a programmer describes an application using C, HDLs take designers to a higher level of abstraction than schematic tools and, in the process, increase productivity, shorten the development cycle and reduce R&D costs. That's a crucial consideration for design teams under relentless pressure to meet shorter time-to-market product windows. It has become even more attractive as FPGA vendors have quickly driven up the densities of their devices from a few hundred thousand gates to today's million-plus gate levels.
HDLs offer other intriguing features as well. They enable designers to functionally verify a design prior to committing it to a vendor technology and, after functional verification, to input the design into a synthesis tool for optimization to a particular device family. Moreover, since high-level textual descriptions are easier to enter and follow than hundreds of thousands of individual interconnect wires, HDLs generally reduce design-entry errors.
|IntelliFlow design environment gives designers access to schematic capture, HDL entry, and finite state machine tools that might be used for design creation. USed with other designing tools, the system facilitates design resuse with a tool that allows simlpe extraction of design elements from a corporate repository. A catalog of designs in schematic or HDL form is readily accessible. |
Despite these advantages, however, many engineers are reluctant to let go of schematic design entry completely. Their caution is well founded. In some cases, a language-based approach can run counter to the best interests of a design team. Schematics typically are used to build the most challenging or timing-critical parts of a design. They still offer the best option when the circuits in a design require performance levels that challenge the capabilities of a vendor's device. With a schematic, designers can optimize the specific details of gate assignments and critical paths rather than letting the synthesis software compile it. These critical paths may contain logical instances that have attributes used to communicate vital placement information to the FPGA back-end software. Using a schematic is a more labor-intensive approach than using an HDL; however, by devoting more time to designing a circuit early in the development cycle, designers can use it to better ensure that their design meets specifications during place and route, resulting in fewer design turns.
Designers opt for a schematic-based approach for other reasons as well. A top-level schematic is easier to read and faster to create than structural HDL code, and lends itself more readily to documentation. Some companies require a level of schematic for documentation purposes to be used in design reviews, for example. Finally, there is the issue of design reuse. Companies have invested man-years in designs that might be applicable to future products. These designs might be highly constrained using vendor-specific place-and-route attributes. Redesigning already working macros by rewriting them in an HDL results in lost time and possibly lost performance.
So while some predict that designers eventually will migrate to pure language-based approaches, a strong argument can still be made for a design methodology that mixes schematic and HDL-based approaches. Rather than being a pit stop on the road between schematic and pure HDL design, a mixed-design methodology offers productivity advantages by allowing engineers to take advantage of each technology. It also allows companies to tap in-house resources and bring together diverse teams of engineers who can translate their respective expertise-in some cases using schematics, and in others through a pure HDL design methodology. The challenge facing designers, however, lies in assembling the tools and methodology needed to implement such an approach.
The first step in building a solution for a mixed-design methodology is to find a process-management tool. Building a design flow around a mixture of schematic and HDL sources coupled with a collection of various schematic capture, synthesis and verification tools can be a daunting task. Complex questions inevitably arise.
If there is a design with a top-level schematic and underlying VHDL and Verilog blocks, for example, how can engineers synthesize language macros and integrate them with the schematic? How do they functionally verify this design or netlist it to get into place and route?
A process management tool should typically provide a single graphical interface for managing everything from design entry and functional simulation to place and route, timing simulation and board-level symbol creation. Ideally, it will understand the mixed formats of the source files in a design and automatically configure tool flows to make the proper conversions between formats. This enables designers to focus on the design itself, rather than on the interaction between tools and, by doing so, increase productivity. By integrating all of the tools through a single interface, a process management tool can help reduce design errors and shorten the development cycle.
With such a tool, the first step in the design flow is to create the design. For example, using IntelliFlow from Viewlogic, designers have access to schematic capture, HDL entry, and finite state machine tools that might be used for design creation. Similarly, by using a schematic-capture tool like ViewDraw, designers have access to utilities that quickly convert language-based blocks into schematic-based symbols.
These symbols can be dragged and dropped into the schematic. To facilitate design reuse, the schematic-capture tool needs to be tightly coupled with a tool that allows simple extraction of design elements from a corporate repository. Using Viewlogic's DxDataBook, a company's catalog of designs in schematic or HDL form is readily accessible for the top-level schematic. Add to this the FPGA vendor-supplied schematic-capture libraries, and engineers have a rich set of resources for design capture.
Once the design is created it needs to be verified, implemented and integrated with the system. To do these tasks, the mixed design is added into the process management tool. This design comprises schematic gates, VHDL blocks and Verilog blocks. Rather than figuring the nuances of how to integrate these various file formats, designers need only to add the top-level schematic. The process management tool would then parse and extract the design hierarchy, recognize the VHDL and Verilog blocks, and automatically pull all required source files into the design process.
At that point, designers would designate the FPGA vendor, product family, die, package and speed targeted. A database built into the process manager typically would supply all data required from the vendor and prevent the selection of incompatible elements.
Before committing the design to place and route or synthesis, designers must verify that their design is functionally correct. Designers building complex mixed-IP designs, however, require a verification environment capable of supporting and integrating all popular forms of design representation.
For example, with a tool such as Viewlogic's Fusion, designers can select from VHDL, Verilog or schematic simulation engines, all integrated into a common simulation and debug environment. Each simulator communicates with the other simulators as the design dictates. The different simulators are run from a common GUI and can be mixed and matched to meet any mixed-design requirements. If more than one simulator is used, the output appears as if a single simulator were being used, with one set of input stimuli and one set of output. Most important, the environment must handle different stimulus types, so that a company preferring to use VHDL for its designs has the ability to simulate a design containing a reused schematic with a VHDL testbench.
After the design is loaded into the synthesis tool, the migration to synthesis, place and route and simulation should be fairly straightforward. Designers can direct the process manager to run the synthesis tool and then feed the netlist created by it into the appropriate place and route tools. With the simulation methodology previously selected, the FPGA vendor's correct tools are automatically selected, ensuring that the netlist will be translated, compiled and loaded into the correct simulator.
Obviously the synthesis tool must support a design methodology that allows the mixing of VHDL, Verilog and EDIF files. Fundamentally, any FPGA synthesis tool must do architectural-specific optimization to ensure high quality of results. This high quality of results translates into faster, smaller designs.
For mixed design, this is not enough. It is important to find a synthesis tool that knows "how to leave well enough alone." In other words, schematic-based portions of a mixed design are usually highly constrained and tuned for place and route, as stated earlier. The mixed design synthesis tool needs to be able to pass through these objects, leaving them untouched and with their attributes intact. This is vitally important because the synthesis tool might try to optimize away logic that is being reused from a previously successful implementation. On the other hand, there are cases of designs being reused in which optimization is preferred because the schematic is not constrained. In that case, it is important for the synthesis tool to have a library that closely matches the schematic-capture library so that elements are recognized and re-optimized.
Executing the process
After synthesis, the process management will move mixed design through place and route. After place and route is completed, the FPGA vendor's tools should output a netlist that is compatible with an EDA vendor's simulator. Viewlogic's Fusion simulator, for example, can handle timing-embedded EDIF, structural Verilog or a Vital-compliant netlist as well as SDF for timing. Static timing analysis ensures that a design is meeting its required timing.
When designers are finally ready to move an FPGA design up and onto the printed-circuit board, it is important to have the process manager provide links to this next level of hierarchy. A critical function is automatic symbol generation. Tools are now available to support multiple mixed-design styles, allowing designers to select the design flow that best suits a particular application and providing the option to reuse existing older schematic designs in a predominantly HDL environment.