Several alternative bus architectures exist in the high-performance embedded computing arena. PCI, VME and VME's secondary buses are a few of the current options, and new contenders have emerged on the horizon in the form of Infiniband from Intel and RapidIO from Motorola. Which one gets designers to where they need to be? Which fit the specific application? How does a developer of large-scale applications choose the right primary bus, and which secondary interconnect provides the maximum throughput?
Currently, CompactPCI and PCI products are chosen for embedded development projects that require small system footprints and modest computing horsepower. These include telephony, medical imaging and document/ graphic imaging. VME and its secondary buses are still the buses of choice for large-scale embedded development projects in defense, military and other demanding environments. Industry watchers predict that VME will continue as the de facto standard in a range of large multiprocessing applications, and in high-speed signal processing projects in particular.
Basically, VME handles the command and control aspects of an embedded subsystem and, in some systems, the low-speed I/O. The secondary buses are dedicated to interprocessor communications and high-speed I/O, and operate over the VME P2 connector. At speeds of 160 to 320 Mbytes/second, these buses give developers the means to move data as fast as today's microprocessors can handle it.
The most widely implemented P2 buses are Skychannel and Race. Front Panel Data Port (FPDP) can provide further I/O capabilities off the front panel of the VME board at 160 Mbytes/s. This bus is especially important to data acquisition applications in which data from multiple channels must be acquired and processed. It can be used in addition to the P2 buses.
When evaluating secondary buses, at the simplest level the determinants can be reduced to current deliverable speed and future upgrade path. The ANSI-standard Race architecture, developed by Mercury Computer Systems (Chelmsford, Mass.), is a 160-Mbytes/s circuit-switch bus with point-to-point restrictions that must be accounted for in the developer's design. While Raceway has an upgrade path to what is now called Race++, with a peak performance of 267 Mbytes/s, there is no easy migration path; developers must buy new hardware and redevelop their program to fit the new architecture.
Skychannel, the 320-Mbyte/s nonblocking packet-switched interconnect, was adopted as an ANSI standard (VITA 10-1995) in 1997. A packet-switched communications architecture, it retains the benefits of a traditional FIFO-based packet bus design, including the reduced connection latency, split transaction, full-speed transfers and guaranteed forward progress. Because of its packet-switched architecture, Skychannel can migrate up to the new standards under development in the marketplace, such as Infiniband and RapidIO for gigabyte performance. In addition, since the FIFOs decouple Skychannel segments, individual segments can run more slowly without degrading faster ones.
Skychannel collects data in variable-size packets and attaches them to a header word that contains the destination's memory address. The address is an absolute one, not a list of routing instructions. It is automatically routed by the hardware to the correct location anywhere in a system based on this bus, including across multiple VME chassis. When the data is originated either by a DMA controller or by a processor performing direct loads or stores, it is formed into packets by a packet controller and loaded into a decoupling FIFO. Skychannel then takes responsibility for delivering the packet to its destination.
Each segment in a Skychannel network can be either a multipath crossbar switch or a shared bus. That architecture alleviates contention by always transferring between high-speed FIFOs, so data travels at the full speed of the data path, not at the speed of the source or destination.
The Skychannel protocol can be implemented over a number of media types at different speeds. The current ANSI specification defines a 32-bit wide interconnect at 80 MHz. However, Sky Computers has implemented 64-bit versions and serial versions. The FIFOs that are already in the Skychannel architecture provide a bridge to higher-speed interconnects such as Infiniband and RapidIO. Both of these architectures use channel and packet technology and promise interconnect performance of 1 Gbyte and faster. However, it will be well over a year before they are implemented in real products. Designers with 12- to 18-month development cycles should be cautioned that these architectures are just beginning to be developed. For the immediate future, designers may want to use the Skychannel interconnect operating at 320 Mbytes/s with the option of easily moving to Infiniband or RapidIO as these products become available. For demanding signal processing applications with significant data acquisition and processing requirements, augmenting the P2 bus with an FPDP solution will enhance the overall productivity of the system and may reduce its overall number of boards.
The Infiniband Trade Association has joined together computing industry leaders Compaq, Dell, Hewlett-Packard, IBM, Intel, Microsoft and Sun in an effort to develop a new common I/O specification that delivers a channel-based, switched-fabric technology. Initially, Infiniband technology will connect servers to remote storage and networking devices, as well as to other servers. It will also be used inside servers for interprocessor communication in parallel clusters. Embedded vendors consider it an efficient way to connect chassis to chassis. Because Infiniband is packet-switched, it is a natural extension of the similar Skychannel architecture.
Leading network companies, including Cisco, Lucent and Nortel, have joined Motorola in establishing a trade association to direct development of the RapidIO architecture. Sky Computers and Mercury Computer Systems are also participating in the RapidIO association. RapidIO provides a growth path from Skychannel because it uses many of that bus's key architectural components, including the nonblocking packet-switch architecture for high-performance communication.
It is too early to predict whether Infiniband or RapidIO will gain the most favor in the market. The two are being positioned as complementary, but will compete for some design wins. Both are extensions of interconnect architectures that have been in development for several years. Both can provide performance advantages. Designers will evaluate them based upon the needs of their individual programs and schedules.