Higher-speed system designs face the ever-present challenge of increasing clock rates. Shrinking the system-clocking period also demands that designers pay heed to more details if they are to preserve the boundaries that define events and the nature of the signal propagation flowing through the system.
Higher clocking rates naturally produce faster edge rates. From a system perspective, the increased edge rates can alleviate a tight timing budget. That comes at a price, however. Faster edge rates mean designers must be more aware of such factors as termination, routing, skew adjust, component placement and zero-delay clock buffering. Addressing those issues properly helps ensure that system integrity is not compromised because of edge or wavefront propagation aberrations. Once considered to involve only esoteric system designs, such issues are now a fundamental part of the high-speed design environment.
To show how wavefront propagation raises complexities at high-signal speeds, we will focus on real examples and concepts of a wavefront propagating from a source to a load. The concept of wavefront propagation might appear trivial at first glance, but visualization of the process reveals complications.
The Test Setup
The setup is purposely simple to build and consistently repeatable. A pulse signal generator drives the board as a 50-ohm source, with a board rise time of approximately 1 nanosecond. The transmission line is constructed on a standard FR4 board with a copper ground plane on the back and a straight, 6-inch trace placed on top. The width-to-height ratio of the trace is constructed to create a 50- ohms characteristic environment to match the source generator.
The load or termination is the system variable to illustrate wavefront activity with different loading conditions. The analysis consists of four options: an open circuit, or high impedance; the standard 50- ohms resistive loading; simple capacitive loading of 8 picofarads, to emulate a typical input load; and, finally, a combined resistive and capacitive loading.
Setting up this example required creating a high-speed probe capable of preserving the bandwidth necessary to see the effects of a high-speed wavefront on the system. The probe needed to have little loading and wide bandwidth, and it had to maintain a low inductive ground return-a tall order by any standard. Through use of good quality coax and a surface-mount resistor, a 21:1 probing system was crafted.
With the setup complete, an analysis of the waveform reveals the fascinating life story of a wavefront as it propagates through the system. The analysis is limited to three sample points along the transmission line starting at the terminating end, then working back toward the source at trace length midpoint, on to the pulse generator source. For purposes of illustration, each trace section is grouped by trace location to easily compare responses under different termination scenarios.
As the wavefront hits the unterminated end, nothing is present to absorb the energy. Because the system is effectively loss-less, adhering to the principle of conservation of energy requires this energy to be returned, or reflected back to the source. The "unterminated" trace captures this event and the response appears as a normal monotonic event. A clock receiver at this position is not a problem.
Now, consider carefully what happens if a clocking receiver is located in the center of the trace length. In this case, the unterminated trace no longer behaves as a monotonic source. Relying on a clocking signal at this position can be downright dangerous. As the incident wave passes through the trace length midpoint, the voltage quickly ramps from zero, then stabilizes at a voltage that is a function of the 50- ohms environment. The voltage will remain roughly at the same level until the wavefront passes back through this point. The delay is the round-trip propagation time.
Upon passing through, the reflected wave continues to add energy, forcing the midpoint to continue its voltage ramp upward. What's seen is the result of a superposition of incident and reflected waves. As we move back to the source, the round-trip delay grows longer and system response is affected further. The danger of placing clock-sensitive components at the source and midpoint is that the input voltage might happen to fall in the logic threshold area. This "midlevel" crisis, of a nonmonotonic nature, could cripple the signal's integrity or, at the very least, significantly reduce the logic threshold margin.
Trace Length Half-Way Point
The story is somewhat different for 50- ohms termination. In this case, the incident waveform arrives at the termination and is completely absorbed. As the 50- ohms termination waveforms indicate, the response flattens out. Because there is no reflected energy from the terminated end back through to the source, the system produces a fixed monotonic ramp. The behavior in this system scenario is expected and controlled.
Turning to look at the capacitive termination reveals further insights. A waveform with an 8-pF capacitive load represents this wavefront. The effects of this load are not immediately obvious until the reflected wave passes back through the center and continues to the source position. This is caused by the low reactance as the incident wavefront passes through the capacitor. This can cause double clocking of devices along the trace.
The final analysis turns to the termination and capacitive-load waveform, where the termination-incident waveform appears normal, with some degradation of the rising edge as compared with the 50- ohms termination waveform. The impact of the capacitor is not apparent until the reflected wave begins its journey back to the source.
The impedance discontinuity caused by the capacitor affects the wavefront in such a way as to cause a profound dip to appear. That is, the reactance of the capacitor causes the wavefront to encounter an impedance lower than 50 ohms. This is displayed as the reflected wavefront moves back toward the source.
The challenges of mitigating wavefront propagation effects in a system and properly dealing with the artifacts are becoming increasingly important as the drive for faster clocking and faster edge rates continues.