A step-by-step design procedure that results in the proper op amp selection and circuit design is given below. This design procedure works best when the op amp has almost ideal performance, thus the ideal op amp equations are applicable. When nonideal op amps are used, parameters like input current affect the design, and they must be accounted for in the design process. The latest generation of rail-to-rail op amps makes the ideal op amp assumption more valid than it ever was.
No design procedure can anticipate all possible situations, and depending on the op amp selected, procedure modifications may have to be made to account for op amp bias current, input offset voltage, or other parameters. This design procedure assumes that system requirements have determined the transducer and ADC selection and that changing these selections adversely impacts the project.
1) Review the system specifications to obtain specifications for noise, power, current drain, frequency response, accuracy, and other variables that might affect the design.
2) Characterize the reference voltage including initial tolerances and drift.
3) Characterize the transducer to determine its salient parameters including output voltage swing, output impedance, dc offset voltage, output voltage drift, and power requirements. These parameters determine the op amp's required input voltage range (V(IN1) to V(IN2)), and input impedance requirements. The offset voltage and voltage drift are tabulated as errors. At this point it is assumed that the selected op amp's input voltage span is greater than the transducer's output voltage excursion. Design peripheral circuits if required.
4) Scrutinize the ADC's specification sheet to determine it's required input voltage range because this range eventually sets the op amp's output voltage swing requirement (V(OUT1) to V(OUT2)). Determine the ADC's input resistance, input capacitance, resolution, accuracy, full-scale range, and allowable input circuit charge time. Calculate the LSB value.
5) Create an error budget (in bits) for the transducer and ADC. Use the transducer/ADC error budget to determine the value and range of the critical op amp parameters. Select an op amp, and justify the selection by creating an error budget for the op amp circuit.
6) Scan the transducer and ADC specifications, and make a set of analog interface amplifier (AIA) specifications
7) Complete the AIA circuit design.
8) Build the circuit, and test it.
Review of the System Specifications
The power supply has only one voltage available, and that voltage is 5V 5% = 5 V 250 mV. The power supply is connected with the negative terminal at ground and the positive terminal at V(CC). This is not a portable application, thus the allowed current drain, 50 mA, is adequate for the job. No noise specifications are given, but the proposed power, ground, and signal traces are being done on high-quality circuit board material with planes and good size copper. A system of this quality should experience no more than 50 mV of noise on the logic power lines and 10 mV of noise on the analog power lines.
This is a temperature measuring system that requires updates every 10 seconds. Clearly, ADC conversion speed or input charging rate is not cause for consideration. The low conversion speed translates into lower logic speed, and slow logic means less noise generated. The temperature transducer is located at the end of a three-foot long cable, so expect some noise picked up by the cable to be introduced into the circuit. Fortunately, the long time between ADC conversions enable extensive filtering to reduce the cable noise.
The system accuracy required is 11 bits. The application measures several parameters so it is multiplexed, and a TLV2544 12 bits resolution ADC has been selected. The temperature transducer is a diode, and the temperature span to be measured is -25C to 100C. The ambient temperature of the electronics package is held between 15C to 35C.
Reference Voltage Characterization
A reference voltage is required to bias the transducer and act as a reference voltage for the analog interface amplifier (AIA). Selecting a reference with a total accuracy better than the accuracy specification (11 bits) does not guarantee meeting the system accuracy specification because other error sources exist in the design. Resistor tolerances, amplifier tolerances, and transducer tolerances all contribute to the inaccuracy, and the reference can't diminish these errors. The quandary here is a choice between an expensive reference and expensive accurate components, or an adjustment to null out initial errors. This quandary boils down to which is the lesser of two evils; expensive components or the expense of an adjustment.
System engineering has decided that they want the adjustment, so the reference does not have to have 11-bit accuracy. A TL431A voltage reference is chosen for the design. The output voltage specification at 25C and 10-mA bias current is 2495 mV 25 mV. This reference has a temperature drift of 25 mV over 70C, and this translates to 7.14 mV drift over a 20C temperature range. There is another drift caused by the cathode voltage change, and this drift is 2.7 mV/V. The supply voltage regulation is 0.5 V, but much of this tolerance is consumed by the initial tolerance and wiring scheme, so the less than 0.1 V is due to regulator drift. The total drift is 7.14 mV + 0.27 mV = 7.41 mV. This yields a total drift of 0.3% maximum. The amplifier usually uses a fraction of the reference voltage, so the final AIA will not drift the full 0.3%.
The temperature transducer is a special silicon diode that is characterized for temperature measurement work. When this diode is forward biased at 2.0 mA 0.1 mA its forward voltage drop is 0.55 V 50 mV, and its temperature coefficient is -2 mV/C. The wide acceptable variation in bias current makes this an easy device to work with. The circuit for the bias calculations is shown in Figure 12.
Figure 12. Reference and Transducer Bias Circuit
The current through RB1 is calculated in Equation 7. Remember, the reference must be biased at 10 mA, and the transducer must be biased at 2 mA.
The value of RB1 is calculated in Equation 8, and the value of RB2 is calculated in Equation 9.
Both resistors are selected from the list of 1% decade values, thus R(B1) = 210 Ohm, 1%, and R(B2) = 1240 Ohm, 1%. The resistor values have been established, so it is time to calculate the worst case excursions of ID (Equations 10 and 11). The resistors are assumed to have a 2% tolerance in these calculations. The extra 1% allows for temperature changes, vibration, and life. Three percent tolerances would have been used if the electronics' ambient temperature range were larger.
The bias current extremes do not exceed the transducer bias current requirements, so the transducer will meet the specifications advertised. The converter is 12 bits and the full-scale voltage is assumed to be 5 V, so the value of an LSB is calculated in Equation 12. The nominal transducer output voltage is 550 mV at an ambient temperature of 25C. At -25C, the transducer output voltage is 550 mV+ (-2 mV/C)(-50C) = 650 mV. At 125C, the transducer output voltage is 550 mV + (-2 mVC)(75C) = 400 mV. This data is tabulated in Table 1.
Table 1. Transducer Output Voltage
The steady state (V(TOS)) offset voltage is 50 mV, thus transducer output voltage (V(TOV)) ranges from 350 mV to 700 mV. The offset voltage is stripped out by the adjustments in the AIA, so it is not of any concern here. V(TOS) spans 100 mV, thus it is a 100 mV/1.22 mV/bit = 82 bit error unless it is adjusted out.
The output impedance of the transducer is equivalent to the resistance of a forward biased diode (Equation 13).
At this stage of the design there are two parameters that influence the accuracy of the measurement, and they are the temperature coefficient of the transducer and the output impedance of the transducer. The temperature transducer has been biased correctly, thus its temperature coefficient should be the advertised value of -2 mV/C. The output impedance of the transducer forms a voltage divider with the input resistance of the AIA, but this error can't be calculated until the AIA is selected. The final transducer error contribution is that portion of the V(TOS) that can't be adjusted out, and this error is determined during the AIA design.
This particular ADC was selected because it has a multiplexer and it enables different modes of operation. The temperature measurement is done in the single-shot mode because this mode allows the user to set the charge time at the input to the converter. During charging, the ADC's input resistance is low, but after the ADC input is charged the input resistance rises to 20 kOhm. This high input resistance does not load the AIA output circuit, thus the AIA achieves full rail-to-rail output voltage swing.
The internal reference is used in this application, and the reference sets the input voltage span required to obtain full accuracy for the ADC. Using the internal reference, the input voltage span is 0 V to 4 V. The offset voltage (V(ADCOS)) is 150 mV, and the voltage drift is 40 PPM/C. The voltage drift over the full temperature range is 40 PPM/C(20C) = 800 PPM. There are 244 PPM/LSB in a 12-bit converter, so the drift voltage error is 800/244 4 bits error.
The ADC output is full scale (all bits 1) when the input voltage is 4 V, and it is zero (all bits 0) when the input voltage is 0 V. This data is tabulated in Table 2. Because the full scale output voltage has changed to 4 volts the LSB is calculated to be 4/(2(12)) = 976.6 V/bit.
Table 2. ADC Input Voltage
OP AMP Selection
It is time to select the op amp, and the easiest way to do this is to list the known specifications or requirements, list a candidate op amp's specifications, and calculated the projected error that the candidate op amp yields.
Table 3. Op Amp Selection
There should be almost no error from RIN because the transducer output impedance is very low. The high side of the op amp's output voltage swing (4.85 V) is much higher than the ADC input voltage (4 V). The low side of the op amp's output voltage swing (0.185 V) is less than the ADC input voltage swing (0 V). The ADC input circuit is 20 kOhm and that doesn't load the op amp output stage, so the op amp output voltage swing is very close to the ADC input voltage range. R(OUT) should present no problems acting as a voltage divider with the ADC input resistance. V(OS) and I(IB) create offset voltages that add to the reference offset voltage, and they have to be adjusted out as a group. The system noise overshadows the op amp noise, thus the op amp noise is accepted unless later calculation prove otherwise.
Amplifier Circuit Design
Enough information exists for the AIA to be designed. The TLV247X op amp is selected because it meets all the system requirements. The first step in the design is to determine the AIA input and output voltages, and this has already been done. These voltages are taken from Tables 1 and 2, and repeated here as Table 4.
Table 4. AIA Input and Output Voltages
The equation of an op amp is the equation of a straight line as given in Equation 14.
Two pairs of data points shown in Table 4 are substituted in Equation 14 making Equations 15 and 16.
Equation 15 is solved and substituted into Equation 16 to obtain Equation 17.
Solving Equation 17 yields b = 10.4, and solving Equation 15 yields m = -16. Substituting these values back into Equation 14 yields Equation 18, and Equation 18 (the final equation for the AIA) is put in electronic terminology.
The circuit that yields the transfer function developed in Equation 18 is shown in Figure 13.
Figure 13. AIA Circuit
The equations for the AIA circuit are given below.
Equation 18 gives the value for m as 16, and using Equation 20 yields R(F) = 16R(G). Select R(F) = 383 kOhm and R(G) = 23.7 kOhm because they are standard 1% resistor values, and this yields m = 16.16. The resistors R1 and R2 are calculated with the aid of Equations 22 and 23.
The parallel combination of R(1) and R(2) should equal the parallel combination of R(F) and R(G) so that the input voltage offset caused by the op amp input current is cancelled. Select R(2) = 105 kOhm and R(1) = 33.2 kOhm because they are standard 1% values, and then b = 10.3. The value of the parallel combination of R(1), R(2) (R(1)||R(2) = 25.22 kOhm) almost matches the value of the parallel combination of R(F), R(G) (R(F)||R(G) = 22.3kOhm), and this is an adequate match for input current cancellation. The downsides of selecting large resistor values for RF are current noise amplification, increased resistor noise, smaller bandwidth because of stray capacitance, and increased offset voltage due to input current. Bandwidth clearly is not a factor in this design. The op amp input current is 100 pA, so it won't cause much offset with a 383-kOhm feedback resistor (38.3 V). The noise current and voltage are calculated later when the error budget is made.
The gain, m, and the intercept, b, are not accurate because the exact resistor values were not available in the 1%-resistor selection chart. This is a normal situation, and in less demanding designs the small error either does not matter or is corrected someplace else in the signal chain. That error is critical in this design, so it must eliminated. There are several nondrift type errors that have accumulated up to this point, and now is the time to correct all the nondrift errors with the addition of adjustments. Two adjustments are used; one adjustment controls the gain, m, and the other controls the intercept, b. The value of the adjustable resistor must be large enough to deliver an adequate adjustment range, but any value larger than that decreases the adjustment resolution.
The data that determines the adjustment range required is tabulated in Table 5. Drift and gain errors are calculated in volts, but drift errors are calculated in bits because they are not eliminated by adjustments. Remember, a LSB for this system is 4/4096 = 976.6 V/bit.
Table 5. Offset and Gain Error Budget
The adjustment for the intercept, b, depends on R(1), R(2), and V(REF). This adjustment has to account for the reference offset, the op amp input voltage offset, the op amp input current, and the resistor tolerances. The offset voltage inherent in the reference is given as 25 mV. The op amp input offset voltage is 2.2 mV; usually op amp offset voltage calculations include multiplying this offset by the closed loop gain, but this isn't done because the offset voltage is adjusted out in the input circuit. The op amp input current is converted to a common-mode voltage by the parallel combination of the reference resistors, so it is neglected in this calculation.
The worst case reference input voltage for the op amp, V(REF(MIN)), is calculated in Equation 24, where the resistor tolerances are assumed to be 3%, and the reference voltage error is 50 mV.
The nominal reference voltage at the op amp input is 0.6 V, so the reference voltage has to have about 40 mV adjustment around the nominal, or a total adjustment range of 80 mV. The nominal current through the voltage divider is I(DIVIDER) = (2.495/(105 + 33.2) kOhm = 0.018 mA. A 4444-kOhm resistor drops 80 mV, thus the adjustable resistor (a potentiometer) must be greater than 4444 kOhm. Select the adjustable resistor, R(1A), equal to 5 kOhm because this is an available potentiometer value, and the offset adjustment is 45 mV. Half of the potentiometer value is subtracted from R(1) to yield R(1B), and this subtraction centers the adjustment about the nominal value of 0.6V. R(1B) = 33.2 kOhm - 2.5 kOhm = 30.7 kOhm. Select R(1B) as 30.9 kW.
The adjustment for the gain employs R(F) and R(G) to insure that the gain can always be set at the value required to insure that the transducer output swing fills the ADC input range. The gain equation (Equation 18) is algebraically manipulated, worst case values are substituted for m and b, and it is presented as Equation 25.
Equation 26 is Equation 27 with 3% resistor tolerances.
Doing the arithmetic in Equation 26 yields R(F) = 19.86 R(G). Thus, on the high side the gain must go from 16 to 19.86, or it must increase by 3.86. Assuming that the low side gain variation is equal, and rounding off to 4 sets the gain variation from 12 to 20. When R(G) = 23.7 kOhm R(F) varies from 284.4 kOhm to 474 kOhm. R(F) is divided into a potentiometer R(FA) = 200 kOhm and R(FB) = 280 kOhm, thus the nominal gain can be varied from 11.8 to 20.2.
Figure 14. Final Analog Interface Circuit
There is no easy method of setting two interacting adjustments because when the gain is changed the offset voltage changes. They quickest method of adjustment is to connect the transducer to the circuit, adjust the offset, and then adjust the gain. It takes several series of adjustments to get to the point where the both parameters are set correctly.
The impedance and noise errors are calculated prior to completing the error budget. The op amp input impedance works against the transducer output impedance to act like a voltage divider. The value of the voltage divider is calculated in Equation 27, and as Equation 27 indicates, the output resistance of the transducer is negligible compared to the input resistance of the op amp. This is not always the case!
The ADC input impedance works against the op amp output impedance to act like a voltage divider. The value of the voltage divider is calculated in Equation 28. The voltage divider action introduces about a 0.009% error into the system, and this is within 13-bit accuracy, so it can be neglected.
The noise specification is given in nV/(Hz(0.5)), and this must be converted to volts. There are involved formulas for the conversion, but the simplest thing to do is assume the noise is wide band. If the numbers add up to a significant error, detail calculations have to be made. The voltage noise is multiplied by the closed loop gain, thus V(NWB) = V(N) (G(MAX)) = 28 nV(20) = 560 nV = 0.56 V. The current noise is multiplied by the parallel combination of R(F) and R(G), thus I(NWB) I(N)(R(F)||R(G)) = 139 pA(22.5 kOhm) = 3.137 nV. The system noise is 10 mV, and this noise comes in through the inputs and the power supply. The power supply contribution is reduced by the power supply rejection ratio, and it is 10 mV/63 dB = 10 mV/1412 = 7.08 nV. This calculation assumes that high-frequency noise is not a problem, but if this is not true, CMRR must be reduced per the data sheet CMRR versus frequency curves.
Some of the system noise propagates through the inputs and is rejected by the common-mode rejection of the op amp. The op amp is not configured as a differential amplifier, so a portion of the closed loop gain will multiply some of the system noise.
The ac gain of the AIA is given in Equation 29.
All of the system noise does not get in on the inputs, rather most of the system noise is found on the power supply. The fraction of the system noise that gets into the ground system and onto the op amp inputs is very small. This fraction, alpha, is normally about 0.01 because the power supplies are heavily decoupled to localize the noise. Considering this, the system noise is 1.18 mV, or less than 2 LSBs.
The op amp output voltage range does not include 0 volts, and the ADC output voltage low value is 0 volts, so this introduces another error. The guaranteed op amp low voltage is 185 mV at a load current of 2.5 mA. The output current in this design is 185 mV/20 kOhm = 9.25 A. This output current approximates a no load condition, hence the nominal low voltage typical specification of 70 mV is used. This leads to a 72 LSB error, by far the biggest error.
Referring to Table 5, notice that the total error is 90 LSB. Losing 90 LSBs out of 4096 total LSBs is approximately 11.97 bits accurate, so the 11-bit specification is met. The final circuit is shown in Figure 14.
Notice that large decoupling capacitors have been added to the power supply and reference voltage. The decoupling capacitors localize IC noise, prevent interaction between circuits, and help keep noise from propagating. Two decoupling capacitors are used, a large electrolytic for medium and low frequencies, and a ceramic for high frequencies. Although this portion of the design is low frequency, the op amp has a good frequency response, and the decoupling capacitors prevent local oscillations through the power lines. If cable noise is a problem, an integrating capacitor can be put in parallel with R(F) to form a low-pass filter.
The final circuit is ready to build and test. The testing must include every possible combination of transducer input and ADC output to determine that the AIA functions in all manufacturing situations. The span of the adjustments, op amp output voltage range, and ADC input range must be checked for conformance to the design criteria. After the design has been tested for the specification limits it should be tested for user abuse. What happens when the power supply is ramped up, turned on instantly, or something between these two limits? What happens when the inputs are subjected to over voltage, or when the polarity is reversed? These are a few ideas to guide your testing.
The systems engineers select the transducer and ADC, and their selection criterion is foreordained by the application requirements. The AIA design engineer must accept the selected transducer and ADC, and it is the AIA designer's job to make these parts play together with adequate accuracy. The AIA design often includes the design of peripheral circuits like transducer excitation circuits, and references.
The design procedure starts with an analysis of the transducer and ADC. The analysis is followed by a characterization of the transducer and reference. At this point enough information is available to make an error budget and select candidate op amps. The op amp is selected in the next step in the procedure, and the circuit design follows.
The output voltage span of the transducer and corresponding input voltage span of the ADC are coupled as two pairs of data points that form the equation of a straight line. The data point pairs are substituted into simultaneous equations, and the equations are solved to determine the slope and intercept of a straight line (an op amp solution). The op amp circuit configuration is selected based on the sign of the slope and the intercept. Finally, the passive components used in the op amp circuit are calculated with the aid of the op amp circuit design equations.
The final circuit must be tested for conformance to the system specifications, but the prudent engineer tests beyond these specifications to determine the AIA's true limits.
Wobschall, Darold, Circuit Design for Electronic Instrumentation, McGraw-Hill Book Company, 1979