The market for "wireless connectivity" is one of the fastest-growing ones in history. This is due to the enormous number of potential applications in communications infrastructure, in industrial and business settings and in an explosion of consumer-oriented uses.
The driving factors in each of these areas are broadly similar, but the consumer area in particular is strongly propelled by continuous reductions in size, mass and power consumption. Most consumer applications involve at least one mobile device, and the portability of that device is critical to making it attractive to the user.
The classic examples of this trend are the gradual shrinking of cordless phones and the even more dramatic size reduction in cellular mobile phones over the past two or three years. But the pressure on size and power is less visible in some other consumer applications, such as adding wireless networking to notebook PCs and PDAs, because the form factor and power consumption are still dominated by the host application.
However, the size of the wireless components may still be an important consideration in fitting the wireless function into the available internal space. With the advent of inexpensive, short-range wireless standards such as 802.11b, HomeRF and Bluetooth we can expect to see a proliferation of new mobile devices with wireless connectivity. For many of these, small size will be the key to portability, or perhaps wearability.
Continuous reduction in size and mass of the semiconductor systems that propel these wireless applications is achieved through several approaches. Increased integration of functionality onto the semiconductor chip has certainly had a major impact. For cordless-like technologies, it is now common for all the active elements-and many of the passives-to have a complete transceiver integrated on one chip. In most cases, all the baseband processing is also done on one chip, sometimes as a block incorporated into the host processor chip. There are many subtle variations of this strategy in the industry, as different suppliers try to find the optimum point in the size-power-performance-cost space for the entire system solution.
Because of the number of variables involved-chip technology, passive technology, system architecture and partitioning, performance requirements, to name a few-it is important to focus on the overall system rather than the individual semiconductor components. What the end-equipment manufacturer wants is a drop-in solution that will deliver the right amount of wireless connectivity to enable the end user to have a stress-free "unplug and play" experience.
The emphasis on ease of use, both for the ultimate consumer and equipment manufacturer, adds to the drive for a second approach to size reduction. Use of advanced packaging concepts can both reduce the size of semiconductor components and achieve higher levels of system integration to make it easier for the equipment manufacturer to quickly bring wireless functionality to its products. This will be especially important in the case of standards like Bluetooth, where in many cases the wireless connectivity is a feature of the overall product rather than the entire point of the product. For example, in a PDA wireless synchronization would be a nice thing to have, but not the whole reason one would buy one.
In many of these applications, the equipment manufacturer does not have any in-house wireless capability and probably has no desire to add it. In such a case, ease of use becomes the most important characteristic of the wireless solution. There is wide acceptance in the Bluetooth community that, in the long run, the main delivery mechanism for Bluetooth functionality will be via some kind of completely integrated module. In fact, the qualification process is set up to take advantage of that expectation. Semiconductor vendors are encouraged to obtain qualification on modules that encapsulate the transceiver or low-level baseband functions or both. The strategy allows equipment manufacturers to reuse the already qualified components and concentrate their own efforts on the higher levels of the protocol stack and on the application. That shortens both the design time and the approval cycle for the finished product.
As a long-time supplier of RF semiconductors, National Semiconductor has pursued a number of approaches to package size reduction and subsystem integration. Over the past three years, we have converted a large portion of our assembly capacity from thin shrink SOPs and thin quad flat packages to laminate chip-scale packaging (CSP). These packages, based on a standard laminate substrate, are about 40 percent smaller than the equivalent leaded package and also have reduced lead inductance. This can be a benefit at higher frequencies. The trend toward smaller packages can be illustrated by the fact that now we are shipping more than half of our RF component volume in CSP, up from zero three years ago. Other vendors are seeing similar trends.
Converting to manufacturing any new package always requires a significant investment in assembly and test-handling equipment. In the case of introducing a whole new class of package, such as the leadless CSP, this is compounded. There is, however, a silver lining. Most of the processing at assembly and test occurs in strip form-that is, multiple packages are processed as a block and are singularized only at the end of the line. This means that new package variants (lead-count or internal connections) can be very easily implemented, since they require only minor modifications to tooling. That allows us to closely match the package to the die size and pin count, giving just about the smallest package possible for any application.
In some cases, we can get even smaller. Micro SMD technology allows package size to be identical to chip size. That assembly process takes place almost entirely in wafer form-it may be loosely thought of as encapsulated flip-chip. The entire wafer is coated with encapsulant on both sides. On the top surface of the die, photolithographic processes are used to open the bond-pad areas, and solder bumps are either placed or plated. The devices are then tested in wafer form and separated by sawing. This is both small and low-cost.
However, its applicability is somewhat limited by the need to ensure that the bond pads are far enough apart to allow the use of conventional pick-and-place equipment by the user. At present, the required bond-pad pitch is typically 0.4 mm or 0.5 mm. For some devices, using this technology would require expanding the die size to meet the pitch requirement, which would increase the chip cost. However, the bumps may also be placed in a rectangular array, which considerably expands the range of chips that may use this packaging technique. We expect to see increasing use of micro SMD for RF components over the next two years.
CSP technologies lead to extremely small form factors for the semiconductor components but do not by themselves address the issue of ease of use. A number of technologies in use achieve system integration of the wireless "node." These range from very well-established printed-circuit board module technology, including the semiconductors and discrete passives, through multilayer ceramic or organic modules that allow three-dimensional interconnect and embedded passive components, and up to novel partitioning approaches in which the semiconductor and passive elements are codeveloped to provide optimum performance and cost.
Many of the established vendors of modules have in recent years introduced laminate-based solutions that incorporate complete radio transceivers in a small form factor. This approach actually has become more attractive with the newer generation of more highly integrated transceiver semiconductor chips as the number of required external components has dropped sharply with the use of newer radio architectures. With this approach, the final size is largely dependent on the total bill-of-materials parts count and the chip-packaging technology used for the key semiconductors. CSP, micro SMD, wire-bonded chip-on-board and flip-chip are all assembly techniques that have been used, or are being explored, to make the smallest possible module.
Multilayer-module techniques, such as low-temperature co-fired ceramic (LTCC) or the laminate-based high-density interconnect (HDI), offer not only excellent interconnect but also the ability to fabricate passive components embedded in the multilayer structure. These can actually be below the active chips, and the consequent footprint of the module can be extremely small. National is producing frequency synthesizer modules for cellular basestation applications based on LTCC; we have also demonstrated a complete radio transceiver in the same technology. Other vendors are also pursuing LTCC module technology, particularly for Bluetooth applications.
Despite the three-dimensional nature of LTCC or HDI, these technologies are still just exotic pc boards in the sense that they use conventionally integrated semiconductor components and provide the remaining passives and interconnection external to the semiconductor chip. A more radical approach is to repartition the system architecture to put more of the passive components into a technology that allows high-performance passives and keep only the active components in the semiconductor.
One candidate for the high-performance passive technology is the so-called glass wafer. Using an inexpensive insulating substrate that is still compatible with conventional semiconductor deposition and photolithographic equipment, this technology allows production of extremely high-quality capacitors and inductors with Q factors as much as 10 times what can be achieved on silicon.
Using this approach, the semiconductor and passive parts of the overall radio subsystem are co-designed to optimize the performance of each part and the overall subsystem. Theoretically, that may provide the optimum combination of cost and performance, but it does have the potential disadvantage of being inseparable. If you want the benefits of this approach, you have to commit to it absolutely. Neither the semiconductor chip nor the passive array will have much value without the other component.
However, with all the elements further integrated on a single substrate, the resulting solution may well be higher-performance and lower-cost than any other while preserving the goal of system ease of use. We are engaged in some early efforts to characterize the capability of such passive-array systems, as are others. It will be one or two years before systems using the technology reach the market.
Other matters relating to packaging of complete systems have to be addressed, including the design and placement of the antenna. A number of vendors are providing embedded or embeddable antenna designs that can be incorporated into a pc board or as an add-on component to a module. All the technologies discussed above could take advantage of such an embedded antenna.
There have even been designs aimed at embedding the antenna into the lid of the semiconductor package. But because of the difficulties of modeling and optimizing the spatial response of the antenna, we expect that for the next two to three years most antennas will be either external or implemented on the pc board or the board module.