The wireless revolution is moving rapidly beyond voice to include such communications-oriented real-time multimedia applications as e-commerce, Internet access, speech recognition, audio and streaming video. As a result, wireless Internet appliances require increasingly complex mobile communications and signal processing capabilities. In addition, while consumers expect state-of-the-art functionality, they continue to demand longer battery life and smaller, sleeker products.
To provide these seemingly paradoxical characteristics-processing power for sophisticated applications with no reduction in battery life-third-generation (3G) wireless multimedia appliances will require designers to think in new ways about the processors at the heart of these systems. Today's processors simply cannot deliver the needed power without sapping batteries to an unacceptable extent.
Emerging applications, such as decoding MPEG Audio Decode, Layer 3 (MP3) audio, real-time MPEG-4 video data streams, and smart speech recognition, challenge the capabilities of the RISC processors commonly used in wireless handsets. It's true that a best-in-class RISC can perform the math-intensive, highly repetitive processing required, but only when it runs full bore and consumes enormous power.
Such applications are more logically served by digital signal processors (DSPs), which are optimized for math-intensive, repetitive operations. A DSP requires significantly less power per clock cycle than does an RISC processor. More important, the DSP needs fewer instructions to implement algorithms, and it carries out more instructions per clock cycle. The result is faster implementation with vastly less power consumption.
But DSPs have their limitations, too. While they excel in the repetitive and complex mathematical operations crucial for multimedia applications, they were not designed to handle the management and control functions that wireless multimedia appliances will demand. As diverse functions come together in 3G appliances, standard processors must converge in a new architecture that integrates an RISC processor with an ultralow-power DSP. Ideally, a software infrastructure should allow developers to partition tasks between the RISC and the DSP to maximize performance without sacrificing battery power.
The need for such a dual-processor approach in wireless multimedia appliances already is becoming apparent. Though current systems do not begin to offer the multifeatured functionality envisioned for 3G, they nevertheless stretch the limits of conventional processing capabilities. As a result, some features in today's wireless equipment don't work well in the typical end-user environment.
For example, the latest smart phones feature speech-recognition capabilities that let the user speak basic instructions. In general, this operates effectively in perfectly quiet surroundings. However, when a user attempts to issue voice commands in a crowded room or in a moving automobile, syllables become garbled and the smart phone fails to execute instructions correctly.
The biggest reason for this failure is that the echo cancellation and noise suppression algorithms used are not sufficient, either because more robust implementations on an RISC processor would chew up battery life, or because the particular processor cannot provide the necessary performance.
Effectively combining an RISC processor and a DSP in one device can provide the processing needed for high-quality speech recognition and audio playback without compromising battery life. In fact, only through the use of DSP technology is it possible today to develop truly speaker-independent speech recognition, in which a wireless handset or multimedia appliance can recognize spoken commands regardless of the user's unique voice characteristics, vocal quality and accent.
Similarly, a hybrid processor can overcome problems that may arise with applications such as MP3 or Advanced Audio Coding (AAC) high-fidelity audio playback. An RISC processor simply cannot provide the signal processing power necessary for these applications without sapping the battery. Programmable DSPs, on the other hand, allow developers to implement any available standard without creating unacceptable battery drain.
DSP, RISC synergy
DSPs provide superior power/performance ratios in applications such as speech recognition and audio playback because these are signal-processing functions, and DSPs are optimized specifically for signal processing. Coupling a DSP with an RISC processor provides access to the capabilities of the DSP, while also accommodating the command and control functions for which RISC processors are best suited.
Employing an RISC processor and a DSP in parallel also solves another problem that will become increasingly annoying as appliances offer multiple applications that may run simultaneously. This is the latency problem that arises when an RISC processor holds up one application to take care of another. In a dual-processor environment, the DSP handles one application's ongoing needs while the RISC takes care of other applications competing for clock cycles.
Some manufacturers already have developed products that employ two separate chips-a DSP and a RISC-to gain the advantages of a dual processor. While the power/performance results generally have been better than those achieved with a RISC processor alone, using independent processors has several drawbacks. Among these disadvantages are the inherently greater cost and board real estate. In addition, two processors use power less efficiently than does a single processor, and the overall system becomes more complex.
Combining two processors on one piece of silicon is not a new idea, and it overcomes some of the disadvantages of the two-processor approach. But physical integration does not equal functional integration, and the possibility that the two processors will not function seamlessly as a single unit remains.
A two-processor approach creates a daunting set of headaches for developers, whether it involves separate chips or physically integrated ICs. Traditionally, DSPs have been much more difficult to program than RISC processors and have required skills that are not widely available, such as assembly language. For these reasons, writing ap-plications for a hybrid processor environment has slowed the development process and stretched time-to-market.
Comprehensive tool sets and software infrastructure can overcome these difficulties by creating a user-friendly development environment. The best approach is one that allows developers to program the dual processor as though it was a single RISC processor. The tools should manage task assignment intricacies and eliminate the need for low-level programming. These capabilities would allow an independent software vendor to create applications that use DSP algorithms, such as MPEG-4, MP3 and speech recognition tailored specifically to the software vendor's needs, such as code space and low power.
As the demands of 3G wireless multimedia appliances compel a move to hybrid processors, the semiconductor industry must meet the need for high-performance, low-power processors that integrate the capabilities of a RISC and a DSP in such a way as to take maximum advantage of the strengths of each. At the same time, the industry and tool developers must find ways to overcome the problems of hybrid processor programming to shorten time-to-market. Functional integration and practical ease of use have become the new priorities. Only by reaching these twin goals can semiconductor makers satisfy 3G wireless appliance makers' thirst for power/performance within the constraints of an increasingly fast-paced marketplace.
While all of this is challenging enough, the needs of tomorrow's market will add even more layers of complexity. The Internet model, which allows users to download and install applications and upgrades quickly and easily, will complicate the equation as consumers come to expect its application in wireless appliances.
Most wireless handsets today are closed systems. But Internet-savvy consumers may not be satisfied with closed systems in 3G wireless multimedia appliances. If the appliance provides Internet access, why shouldn't they be able to download an application when they want it?
Providing the ability to download and install applications requires broad acceptance of standard operating systems such as Windows CE and Symbian Epoc. A combined RISC and DSP multimedia wireless processor ought to be designed so that it can be ported to these operating systems or any others that may emerge as standards.
At the same time, processors targeted to 3G appliances ought to open up systems by offering architectures that are widely available, not only to OEMs, but also to third-party developers. In today's closed systems, third parties can create applications only by working closely with a particular handset OEM to understand the intricacies of proprietary designs. A vendor who hopes to reach the broadest market faces the discouraging prospect of developing multiple applications for different closed systems, all of which, presumably, do the same thing.
Not only does this arrangement work to the detriment of third-party developers, it also limits OEM access to innovation. Some features may die on the drawing board because closed systems limit market opportunities. Or an OEM may lag behind in getting to market with features similar to those developed for a competitor by third-party vendors.
From the consumer's viewpoint, new applications from whatever source ought to be available for downloading. Many users don't mind paying for the latest bell or whistle, but most will object to replacing an entire appliance merely because the one they purchased cannot deliver the functions they want. For some OEMs, ASICs have provided partial solutions to these problems, but the associated long turnaround times and high cost can be prohibitive.
Because today's DSPs are fully programmable, a dual processor allows OEMs to enhance existing systems and sell new features without replacing basic hardware. Today's marketplace allows little time for the design and manufacture of new silicon to accommodate new standards and protocols, provide innovative features and functionality or eliminate bugs.
Equipment manufacturers, semiconductor makers and third parties must still address several areas of concern. At the very least, the most pressing needs include a dual-processor architecture that allows both a RISC and a DSP to perform the tasks each handles best. This will optimize power/performance; functional processor integration; adaptability to the Internet model; easy porting to standard operating systems; an open architecture that encourages third-party developers; and rapid time-to-market.