Programmable ICs provide the building blocks for making software-defined radio platforms a reality. The programmable flexibility to use a single up- and downconverter chip to support multiple transmission standards-including Advanced Mobile Phone Service (AMPS), Nordic Mobile Telephone, Global System for Mobile Communications (GSM), IS-136, Enhanced Data Rates for GSM Evolution (Edge), IS95, TD-SCDMA, CDMA2000-1X/3x/3x DS, W-CDMA and UMTS Terrestrial Radio Access-is now possible, whereas previous hardware platforms were limited to specific frequencies and signalprocessing formats.
The result is the design simplification of both the transmit chain and the receive chain, which advances base transceiver station equipment from being hardware-constrained to being capable of supporting software reconfiguration of multiple air interfaces.
Programmable up/downconverter ICs are making the jump from being hardware constrained to software configurable by integrating the baseband-to-intermediate-frequency components into single-chip solutions. New four-channel digital upconverter ICs provide serial or parallel 16-bit interfaces, FM modulators, 48-bit sample numerically controlled oscillators, 32-bit carrier NCOs, 256-tap shaping finite impulse response (FIR) filters, half-band filters, high-order interpolation (HOI) filters, gain profile and gain control, with dynamic channel allocation and 20-bit output buses controlled by a microprocessor interface.
New four-channel digital downconverter ICs provide four 16-bit parallel inputs, 32-bit quadrature carrier NCOs, 1-5 stage cascaded integrator/comb filters with barrel shifter gain, half-band decimation and interpolation filters, 256-tap FIR filters, 192-tap resampling FIR filters with 56-bit timing NCO, automatic gain control (AGC) and output select, format and serialize functions controlled by a microprocessor interface.
Typical of the new generation of upconverters is Intersil's ISL5217 quad programmable model, a single-chip replacement for the serial-to-parallel converters, low-pass filters and analog quadrature upconverter components of earlier designs. The IC interfaces the host processor to the D/A converter, providing a highly reconfigurable signal-processing block capable of 100 dB of spectral purity and more than 140 dB spurious-free dynamic range (SFDR).
The flexibility of many new software-configurable upconverters begins in the front-end data input path. Data enters the chip at the sample frequency (Fs) in either serial or parallel format. Serial sample data bit lengths of 4, 8, 12 or 16 bits can be selected with adjustable time slot counters controlling the latency in relation to the frame strobe request for data. The integration of microprocessor interfaces allows both real-time device configuration control and 16-bit parallel sample data input directly into individual channel memory space. Data flow rates in excess of 6.5 million samples per second can be supported by the chips and can be clocked (CLK) as high as 104 MHz.
The front-end data routing path is configurable for multimode operation to support IS-136, Edge and IS-95, which require vector modulation; AMPS and Nordic Mobile Telephone, which require FM with band limiting filtering; and GSM, which requires FM with pulse shaping. The sample data can be routed between the shaping filter and the FM modulator to support each of these standards. Typical individual I and Q shaping filter implementations are fully programmable for both the interpolation rate and the data span. This is achieved by selecting four-, eight- or 16-times interpolation phases and four to 16 DS settings to produce an IP x DS, or 16- to 256-tap shaping filter. Advanced features for the shaping filter include a dual memory partition, allowing for the preloading of two 128-tap filters that are selectable by programming a single bit in the device control word, and the selection of either 16-bit 2s complement or 24-bit floating point coefficient formats.
The FM modulator provides frequency modulation of the carrier center frequency by the input data with 18-bit accuracy. The modulation type selection, which controls the FM and shaping filter routing order, is controlled by the setting of two additional bits in the same control word and provides time-division multiple access (TDMA) overlay of GSM with Edge in sequential bursts within a single TDMA frame. Reprogramming within the guard time duration is achieved in support of this multimode operation.
Data exits the shaping filters into the gain profile and gain control stage at the (Fs) x IP rate. The GSM burst mode time mask requirements are implemented through a user-controlled gain profile 128 x 12-bit RAM memory and a programmed gain profile length. The gain profile coefficients are linearly multiplied with the shaping filter output data to perform the profiling. The transmit enable signal (TXEN) can be input externally or programmed and generated internally, with the gain profile length providing the number of symmetric ramp-up/-down steps in relation to the rising and falling edges of TXEN. The user can load new gain profile coefficients without taking the channel offline, to control gain profile edge latency and to bypass the gain profile. Gain control is implemented through a scaling multiplier followed by a scaling shift. This combination provides -0.0026 to -144 dB full scale of attenuation with 12-bit resolution.
To improve the SFDR by rejecting the images produced within the shaping filter a fixed coefficient half-band filter is implemented following the gain control. This interpolate by 2, 11-tap filter with coefficients of 3, 0, -25, 0, 150, 256, 150, 0, -25, 0, 3 is typically 20-bit throughput with data exiting at the (Fs ) x (IP) x (2)rate.
The shaped sample data is input into an HOI filter that resamples the data from the input rate to the final clock rate. Both integer and noninteger interpolation rates are supported by integrating a highly precise 48-bit sample NCO into the channel design. The NCO is programmed so that the most significant bit is the sample frequency, Fs, which controls the movement of the sample data from the input to the shaping filter. The coarse phase of the NCO controls the processing of the shaping filter and the fine phase controls the processing of the HOI filter. The output from the HOI filter is always at the final clock rate. Special features of this stage include a programmable leap counter for realizing fixed integer interpolation and preventing symbol slip due to the accumulation of phase error and a synchronization output to provide multiple device operation.
As older radio designs utilized separate I and Q D/A before quadrature mixing, the incorporation of separate and identical processing paths for I and Q have led to the movement of the complex mixer from the analog domain into the digital sphere. Complex mixers are now common after the interpolation stage, with 32-bit carrier NCOs allowing precise digital control of the channel center frequency. Being able to program the carrier from -CLK/2 to +CLK/2 provides vector rotation control. New features include the ability to preload the carrier phase offset with 16-bit resolution.
To support smart antenna functionality through sectorization and beam steering, four dynamically switchable 20-bit output buses are provided with eight selectable data output formats. Cascade, real, imaginary, muxed I/Q, muxed I/Q at 2x and three complex I/Q modes are selectable, in addition to the ability to route any of the four-channel inputs to any of the four-output summers. This provides channel format and routing control at up to a CLK/4 rate.
As makers of base transceiver stations begin implementing multicarrier power amplifier and predistortion technologies in their equipment, the advantages of these new four-channel devices will be realized as the cost-reduced narrowband multichannel architectures significantly decrease component counts and create transmitter platforms that are truly software configurable. As the implementation of wideband architectures progresses, the use of the new upconverters in combined channel or polyphased modes will demonstrate the overall programmability of these components.
A typical scenario would be a W-CDMA implementation of a UMTS Terrestrial Radio Access channel supporting a chip rate of 3.84 million cycles per second, a channel spacing of 5 MHz, a channel raster of 200 kHz and adding a 61.44-MHz clock constraint to demonstrate the ability to combine channels. To have sufficient clocking, the device requires CLK > (Fs x IP x DS), which, at 61.44 MHz and an Fs of 3.84 MHz, would allow only 16 taps-not enough filtering for a single-channel implementation.
Combining channels to reduce the Fs rate to (Fs/number of channels combined) allows designers to obtain 61.44 MHz > (3.84 MHz/4) x DS x IP, or 64 taps. This is effectively reduced to 48 taps as the data is recombined by the summer before output to provide the effective filtering required.
Intersil's HSP50216 Quad Programmable Downconverter, a single-chip replacement for the oscillators, mixers, bandpass filters and AGC circuitry of earlier radio designs, exemplifies the analog-to-digital evolution of downconverters. This IC interfaces the A/D converter directly to the host processor, providing a fully programmable signal-processing block capable of 110 dB of FIR out-of-band rejection and more than 115 dB of SFDR.
To facilitate the increasing performance of today's A/Ds, data input is accomplished through four independent 16-bit parallel input buses with either fixed- or floating-point formats to support standard and gain ranging A/Ds. Each input can be routed to any of the four channels, with gated, interpolated and multiplexed data input modes supported. The interpolated mode allows for zero samples to be inserted between A/D outputs to interpolate the input data stream up to the clock rate. Input in fixed-point offset binary or 2s complement format is allowed, with the ability to select one of up to eight multiplexed data streams.
After the input, the data is routed to the NCO-mixer-CIC (cascaded integrator/comb) stage, where a programmable 32-bit quadrature carrier NCO is mixed with the incoming data to perform the down-conversion into I and Q components. To ensure adequate noise floor, overall spurious performance and enough tuning resolution, the phase quantization to the sin-cos generator is 24 bits and the amplitude quantization is 19 bits. Advanced features are provided, such as a built-in pseudo-noise generator that effectively increases the noise figure of the receiver by reducing the input sensitivity and adjusts the receiver range. The CIC is an effective architecture for decimation filtering of the resultant data, with the order being programmable from 0 to 5 and a required minimum decimation of four.
From the CIC, the data flows into the back-end processing stage where a dual multiply-accumulator filter compute engine (FCE) with a microcoded FIR sequencer, a FIFO-timer for evenly spacing samples, a 0- to 96-dB AGC and a Cartesian-to-Polar coordinate conversion block are available. The FCE also accepts a data recirculation input for cascading filters and a magnitude and phase feedback path for AM and FM filtering that is based on the implemented air interface. At this point, the flexibility of the digital components becomes evident, since the FCE can be coded to implement different types of filter architectures that consists of decimating half-bands, shaping FIRs, interpolating half-bands, resampling FIRs and other complex filtering schemes that are controllable by the 16-bit microprocessor device configuration bus. The only limitation on configurability is the number of available clock cycles, the RAM and ROM resources and the imagination of the system architect.
Continuing the previous example, the FCEs of all four channels are utilized to provide effective receive filtering of the transmitted signal. The channel 0 front end is used to down-convert the data and its CIC filter decimation by four. The channel 0 FCE performs the initial filtering with a 10-tap imported FIR and decimates by an additional factor of two. At this point, the received data is routed to the remaining three channels and is programmed with differing delays to allow each channel to utilize a 38-tap FCE FIR filter. Data is output from the device at 7.68 million samples/second (2x) by using the output-selection routing to output Channel D, C and then B in a recombined format.
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