One of the features required in new digital TVs is a simple recording and playback system for compressed MPEG video streams that enables the smooth execution of "trick plays." Examples of trick plays are fast or slow forward, fast or slow reverse, or pause.
Smooth trick-play execution is the most crucial function in the design of a recording and playback system for compressed MPEG video streams. The playback controller in such a system, which records and plays back trick plays, requires significant computational resources. Those resources must be dedicated to transport stream decoding, stream index generation, coded picture reordering and reconstruction of the stream.
In a storage system such as a digital videodisk, the stream has some information for trick plays. DVD streams are created for storage media. They include some picture information for trick plays for example, the number of pictures and the position of the picture in the stream. But a broadcast stream has little or no information about them, so for a trick play, information must be created during the period in which the stream is recorded.
A stream index generator creates the index, or picture information. Each index entry is made up of a transport stream (TS) packet number including the picture start code, which shows the picture's position in the stream, and the picture coding type, which can be an I-Picture, P-picture or B-Picture. The controller can reorder the recorded stream based on the index, so the system can execute the trick play smoothly.
In order to perform trick-play functions in the recorded program, or stream, the CPU must analyze the stream, then collect some basic information during the recording. In addition, the CPU must execute TS decoding, coded picture reordering and TS reconstruction at playback. Using that CPU-intensive methodology, the execution for some kinds of trick plays (especially reverse play) requires plenty of processing power.
The unbalanced reliance on CPU power for reverse plays can be reduced with the use of a device that is fully equipped with specific function blocks dedicated to stream recording and playback. A single-chip MPEG-2 decoder IC that enables digital stream recording and playback is needed to achieve this simultaneous functionality most efficiently. The decoder IC should include specific MPEG-TS recording and playback functionality for trick-play execution.
Based on its experience in first-generation MPEG-2 decoder technology, Fujitsu designed the kind of highly integrated MPEG-2 device needed to meet those requirements.
The IC, based on more than two million gates in a 10.8- x 10.9-mm area, includes a transport stream decoder element, which diffracts the transport stream; a video decoder element, which decodes the MPEG video stream; a format converter element, which enlarges or shrinks the display image; an on-screen display (OSD) element, which handles all graphics display; and the memory element, which controls external synchronous DRAM and other memory requirements.
In designing such a device, emphasis needs to be placed on decoder reusability. The more independently each block can operate, the more easily block performance can be improved and features added.
The video decoder unit is able to decode one HDTV stream, or up to four standard-definition TV (SDTV) streams simultaneously, while supporting the execution of trick plays. The display unit is able to convert any source format into any display format, including de-interlacing with motion estimation. As many as four graphics layers with a video plane can be blended or overlaid using the OSD unit. The multidecoder, multidisplay function enables users to set up a layout that can accommodate various input streams and viewing.
The video decoder element handles MP@HL single decoding and MP@ML times four channel multidecoding. The format converter element enables simultaneous display of as many as four screens, along with at-will enlargement, reduction and overwrap display for each screen.
To resolve the critical record-playback requirement and efficiently execute trick plays, the new device provides dedicated functional units that can record or play back MPEG-TS, using a partial transport stream generator that extracts any programs selected from a stream that contains multiple programs.
A stream index generator makes index entries for extracted MPEG streams. Each index entry includes a packet number that provides the picture start code and the picture coding type. In addition, a trick-play assistant unit masks invalid data that is formed when two discontinuous TS packets are connected.
The DTV receiver can complete trick plays (except for fast forward) by recording the broadcast stream and an index generated by the IC in the hard-disk drive. The controller immediately sends the trick-play stream from the drive to the IC. The reverse play of the live stream can be viewed, and the IC can decode and display both the live broadcast stream and the recorded stream simultaneously.
At the recording stage, the partial TS generator extracts the selected program for a multiprogram TS, and the stream index generator makes index entries for it. The stream entries are recorded in the stream recorder which is in an external hard-disk drive. And the index entries are recorded in a playback controller in a CPU. At playback, the controller has only to reorder TS packets according to their index entries without analyzing the stream.
Invalid data that exists between two discontinuous TS packets is masked by a trick-play assistant unit in the device, so the video decoder can decode the stream without creating any syntax errors.
Most kinds of trick plays can be executed by the playback controller, based on the unique stream index entries generated by the device. Among them, the reverse play demands the highest processing power about four times the power required for forward play. The Fujitsu device has been designed specifically to enable smooth execution of reverse play for a conventional SDTV stream.
As DTV moves into the mainstream and consumer demand rises, so will the requirement for a highly integrated single-chip decoder that can execute trick plays simply by reordering TS packets in a CPU. And the less processing power needed, the better the system will perform.