The mission of the CoDesign Methodology for System and Architecture (CMSA) team at STMicroelectronics is to provide system-level design support to several divisions for video, set-top-box and wireless applications. As part of this effort, the team provides the appropriate model support at different levels of abstraction for generic intellectual-property (IP) models like the STBus and the ST100 processors.
An integrated system-level-to-implementation design flow must meet several requirements. It has to be based on commercially available EDA tool environments and translators, or co-simulation engines must be available to bridge gaps between abstraction levels and tools. Generic and specific IP model libraries have to be developed to shorten the path to the initial behavioral and architectural model of the system and its testbench, which will be shared by all the tools. IP models like buses and processors need to be equipped with performance models to allow high simulation speed sufficient for architecture exploration and system tests.
A project to provide the essential models for a system-on-chip (SoC) platform has been initiated as a collaboration between STMicroelectronics (Grenoble, France) and Cadence Design Systems (San Jose, Calif.). In the first phase, instruction set simulator (ISS) models of the ST100 DSP have been integrated into the Cadence Virtual Component Co-Design (VCC) environment together with the associated debuggers and compilers. In addition, a VCC model for the STBus has been specified, developed and its performance characterized using bus-cycle accurate (BCA) modeling in the CoWare N2C infrastructure. Finally, a link to CoWare N2C is currently being developed, including block and architecture export to N2C from VCC models via VCC communication synthesis.
The Cadence VCC environment has the ability to estimate the performance of functions mapped into software. An ISS model of the ST100 DSP has been integrated into VCC. The goal is to provide more accurate performance estimation for software blocks, while maintaining abstract, higher-level communication channels at the block boundary, which uses a Post(), Value() and Enable() discrete-event model of computation. The processor model provides cycle counts and memory delay information. Memory references and bus traffic are accurately generated by the ISS, and transactions are executed within the VCC architectural service infrastructure.
Functionality and architecture in the VCC environment are modeled separately and design experiments are defined using mappings between function and architecture. All functions mapped to software are automatically compiled and linked to the processor ISS model together with a scheduler calling the appropriate functions when they are triggered in simulation.
Because buses are key components of SoC platforms, bus performance and arbitration can be modeled in the VCC infrastructure. STMicroelectronics has developed a full crossbar bus that combines distributed system advantages and standardized communication path flexibility without being limited by huge arbitration overhead and poor overall communication bandwidth.
To maximize the flexibility for architecture exploration, the STBus is modeled in VCC as an architectural model generic enough to be completely independent of the application. The objective is to enable a continuous flow, avoiding gaps between VCC and N2C. This flow allows architects to explore and evaluate architectures with different models and buses in VCC before going to a BCA C platform in N2C.
The design export from VCC to N2C is a four-step process: First, each hardware-mapped block is translated to a BCA C block. Then each block that is mapped to an RTOS will be compiled and loaded on dedicated memories interfacing the ISS. Next, probes are translated to be used in VCC visualization. Finally, the CoWare N2C system is generated. VCC Communication Synthesis is a process in which the VCC export assembles the implementation of communications between behaviors, and the method used to support the Bus Patterns.