Developers of voice and data communications systems face twin challenges. They must meet ever-expanding bandwidth requirements, yet design testable, manufacturable and reliable hardware. New systems that repeatedly switch multiple channels of high-speed information are particularly vulnerable they demand thorough planning to both meet the design objectives and remain manufacturable. The high-frequency serial and parallel interfaces between subsystems require significant attention to ensure signal integrity; there is simply no room for skew, noise, jitter, offset or delay.
Bench evaluation of these critical interfaces in controlled environments is routine. One only needs to make sure there is a thorough and affordable test solution in a production assembly environment. The current problem is to find a way to plan for the test requirements of these interfaces during the design process; the solution is to use a methodical system-level approach to design-for-test (DFT) based on the IEEE 1149.1 Standard for Boundary Scan Test.
DFT teams can take advantage of a large variety of standardized test insertion tools offered by both hardware and software vendors that support 1149.1. Semiconductor vendors provide 1149.1 test access to digital IC's of all types: buffers, ASICs, DSPs and systems-on-chip. Automatic-test-program-generation software tools produce test vector files from the design netlist. Off-the-shelf PC-based hardware lowers the cost of driving test vectors to the system and interpreting the results.
Furthermore, 1149.1 doesn't just support digital test. Many IC vendors are supporting this test bus as a standardized way of programming flash memories or configuring complex PLDs. And now the high-speed serial links can be tested using the 1149.1 bus to initiate embedded built-in-self-test (BIST) sequences and to report the results.
Many new designs are looking toward low-voltage differential signaling (LVDS) as the keystone for routing high-speed signals throughout the system. LVDS is a very robust interface standard and can be used to communicate across the backplane and between boards at high speeds with serial links. The high speed serializer/deserializer function is becoming popular for moving parallel digital data across a low-cost serial cable between cards in a system. The serializer takes multiple digital signals and serializes the data into a single bit stream with an embedded clock; the deserializer recovers the clock and the embedded data from the bit stream for further processing.
This presents some interesting challenges to the test engineer. Pure functional testing of these interfaces provides limited fault coverage at best. Introducing external signals to the interfaces for testing is cumbersome and unsuitable for a production environment. The 1149.1 standard is effective for detecting the typical "stuck-at" faults on the TTL sides of the serializer/deserializer, but since it was primarily developed for digital test, only a limited fault spectrum can be detected in a mixed-signal environment.
Furthermore, at high frequencies the LVDS driver, receiver and cabling must be modeled as a transmission line, presenting frequency-dependent losses that are difficult to detect (see Fig. 1). A distressed cable, improper terminations or poor board layout can often pass testing at slow speed, yet fail if the speed is increased. And finally, failsafe features included in the receiver can frequently mask problems with interconnects until they are operated at higher speeds.
The best solution is to embed the test capability directly into the serializer and deserializer. This eliminates external loading from ATE or other equipment, so the environment remains "pure." A BIST mode used to trigger an embedded bit-error-rate-test in both the driver and receiver can be initiated and verified externally through the 1149.1 bus. The driver and receiver are loaded with a BIST instruction through the 1149.1 port and the test is initiated simultaneously in the driver and the receiver. The driver sends pseudo-random patterns of data at the system clock frequency across the high-speed interconnect and the receiver compares the incoming pattern to the expected value. Both devices contain the same pseudo-random algorithm. Once the BIST is initiated, the receiver is monitored via the 1149.1 port to detect a BIST_Complete and Pass/Fail bit. This BIST technique gives complete test coverage for the entire signal path in a nonintrusive manner.
An investment in DFT and 1149.1 solves more than manufacturing problems. Once the infrastructure to support the standard has been incorporated into the system, there are new opportunities for further advancing the system capabilities. Many vendors of complex PLDs, FPGAs and memories are supporting the use of 1149.1 for serial access to program or configure these devices. The 1149.1 bus can be used for in-system programming during manufacturing, for power-up refresh and for firmware upgrades once the hardware is fielded. Connect all these systems and the test capability to an Internet Protocol address and then you can remotely monitor system status, initiate test sequences or upgrade software or firmware revisions.
Evaluation of high-speed-signal integrity is a critical part of a system test strategy. Mixed-signal test requirements are widening the scope of the well-established 1149.1 digital test practices and capabilities. A comprehensive DFT plan can support test requirements at all stages of development, from debug of initial prototypes and production yield enhancement programs to supporting fielded systems. Solutions that build upon industry standards are well understood and supported and provide a cost-effective approach to a testability road map that supports a long-term philosophy for meeting future challenges.
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