With the rapid growth of the communications market has come the concurrent implementation of complex tree structures for clock distribution. Clock trees are needed to feed the many nodes that these, and other, designs required to move data through many different functional design blocks with digital time domain precision. With this requirement for large numbers of clocks to time multiple nodes in these systems also comes the responsibility to create these timing clocks within tight and very precise and constrained windows time.
These windows are measured, currently, in Pico-seconds (1x10^-12 second). With the magnitude (quantity) of nodes that must be fed and the rapidly decreasing timing windows that the clocks must be placed within, designers must understand the nature of the devices that create, multiply and transport these clocks. To add another level of complexity to the clocking system, many of today's clock generating and transporting products contain PLLs. These PLLs provide the designer with the luxury of re-timing late or early clocks, eliminating the propagation delays that occur when clocks are transported over long distances and the ability to produce clocks of different frequencies that are phase locked to a reference clock.
With these PLL enabled clock manipulating abilities comes a PLL penalty of responsibility. That is to understand and allow for the signal degradation that all PLL based clock processing components produce. While the "noise" that PLLs add to the clocks they process cannot be totally eliminated, it can usually be tolerated and the components in the clock tree that have PLLs in them can be configuration controlled to the point that the noise they create is managed and the overall clock tree performance will be well above minimum acceptable limits.
The noise that PLLs add or impose on the clock signals they pass or create is cumulatively known as jitter. In electrical terms jitter is the variance of a defined clock point (usually a rising or falling edge at a specific voltage) from its absolute desired point in time. This jitter is classically divided into 2 major groups. The first is the short-term jitter. It is measured by the movement of the point from its ideal position in adjacent clock cycles. The common term for this parameter is "Cycle-to-Cycle" jitter.
The second type of jitter is measured over a longer period of time. A poor term for it is "Long term Jitter." The more commonly accepted and accurate term is "long term period jitter." In this area, a length of time (in cycles or seconds) must be specified to bound the period that the event is sampled over to produce the measured value. Given an infinite period of time the event would wander over an infinite position so we must set and state a measurement period that we are measuring the events occurrence over to more precisely define how a measurement is being taken. This is usually relevant to how stable the edge must be within a specific period for a specific application.
In the process of building clock trees of any reasonable magnitude, the placing of PLL based clock processing components in series inevitably occurs. When this happens, the question of how the jitter that is caused by each of these individual components interacts with each other and, even more important, what will be the jitter content of all the final product clocks the tree creates. This article addresses this in an over-all conceptual and functional effort.
When engineers approach designs that incorporated multiple PLL clock processing devices connected in series, they are usually confronted with two sources of information. The first is the RF designer's legacy of knowledge. While there is a wealth of information on RF PLL-based designs they are usually involved in circuits that mix two PLL-based signals to produce a sum or difference clock. Also, they usually do not contain timing limitations in the picosecond range ad digital designs do. In the digital clock area a lot of theoretical information is available but what a designer needs is some empirical information or proof to convert this applications mumbo-jumbo into a clear straight forward views of what to expect and where to concentrate his design time and resources to produce a robust design.
In this article we are going to look at the performance produced by of a specific, but typical experiment using five PLLs connected in series. While designing five PLL devices in a series configuration is not advised, it is specifically being used here to accentuate and amplify the effects that we are interested in.
The first point to be understood when looking at PLL based clock processing components is how they appear to the clock signal that must pass through them. Figure 1 shows a typical ZDB (zero delay buffer) components and it's constituent parts.
Figure 1. Phase Lock Loop (PLL).
Of most electrical significance is the series connected group comprised of the phase detector, error amplifier, charge pump and loop filter. To an incoming reference clock these components appear as a second order low pass filter. Figure 2 illustrates the jitter and frequency transfer functionality and thus the bandwidth response of the devices we used in this example.
Figure 2. A Typical jitter transfer curve of a zero delay buffer.
This is an input to output transfer function graph. It indicates the gain (and loss) of any incoming frequency to the component. Notice that incoming frequencies (either by themselves or riding on top of the incoming reference signal) will be passed through and amplified by the loop filter and phase detector combination of stages. Frequencies (and frequency components of complex waveforms) above the 1.5 MHz rolloff point will be attenuated by this filtering action and therefore suppressed and reduced as they pass through this device.
To analyze and explain the effects that the PLL clock processing devices have on the clock signal that passes we will look at the noise that is present on these clocks, as they pass through successive stages, in three distinctive views.
The first will be a frequency domain view. In this we will be using a spectrum analyzer to see the power level verses frequency plot of how this noise propagates through the system.
Secondly we will look at a long-term period jitter view. Here we will see how the output clock acts over a longer period of time and the actual distribution of these cyclical variations by frequency. This measurement will show an occurrence (population) quantity against a frequency scale using a TIA (timing interval analyzer)
The third will be a modulation domain view. Here we will see the cycle-to-cycle (C-C) or adjacent cycle frequency change for a medium length series of cycles. This will show us the impulse or immediate frequency (jitter) presence as well as a view over a medium period of time.
The part used for this article had the following data sheet characteristics
200 pSec C-C jitter
1 MHz PLL loop bandwidth
Figure 3 shows the resulting frequency domain view. Knowing that the part has a little over 1-MHz loop bandwidth (per Figure 2) explains the results shown here.
Figure 3. Like PLL's in series (Frequency Domain view).
The waveform numbers shows the fundamental energy content of the reference clock to the first stage. Notice that there is a fairly flat noise floor on both sides of the reference carrier frequency. The width and slope of the carrier trace is due to the Video and resolution bandwidth setting of the spectrum analyzer. It is important to note the flatness of the noise floor to the sides of the reference clock, as we will be focusing on how they change from stage to stage.
If you will remember from figure 2 we showed and stated that the PLL based clock devices act as low pass second order filters in the frequency domain. Figure 3 positively affirms this fact. As we look at the spectral content of each succeeding stage we can clearly see that noise that is within the passband of the loops filter is passed and amplified more and more in succeeding stages. In fact we can clearly see that for the output of the second stage and later that there is a definite peaking of the spectral energy passing through these stages. This corresponds to the slight peaking at the edge of the passband that is seen in figure 2. Of secondary interest is the noise floor beyond the bandpass of the devices. Notice that even after five stages of gain it remains relatively close to the input signal (far top and bottom) levels of the waveforms amplitude.
The information that can be derived from this view is that the device does in fact act as a low pass filter to frequencies around the reference frequency. Low frequency (close to the carrier) energy and signal components will pass through the device with ease. This means that this low frequency energy, which translates in performance to a low frequency and slow movement or wandering of the output frequency will be passed or amplified as the signal passes through successive stages. What will control its final magnitude (deviation from the input reference to the first stage in frequency) depends almost solely on the bandwidth of the devices and any other attempts to suppress it between the stages of the tree.
The second view we will look at is very long term or period jitter view. Here in figure 4 we are looking at the stage to stage progression of jitter over a much longer period snapshot of time. In this cans many seconds.
Figure 4. Like PLL's in series (delta Period Jitter View).
Shown in each figure is the output histogram plots of a Timing interval analyzer (TIA). In the plots show frequency on a horizontal scale and the relative number (quantity) of output clocks that populated that specific frequency. Of immediate notice is that the population spread is Gaussian in nature. This supports the known fact that random jitter, caused by the actual noise inside the component or the white noise inherent in the input signal, will exhibit itself in a highly predictable Gaussian distributed spreading (frequency modulating) effect on the signal. Of secondary notice, is that the effect on the total magnitude that this noise has over multiple stages, is that it accumulates and widens (exists over a wider frequency range) as it passes through each additional stage.
Note that these frequencies are close in to the fundamental one. This supports the previous view as it shows that in close (or within the devices bandpass) noise and energy components are not only passed by each device they are amplified. Again this noise (jitter) is close to the devises operating frequency so the rate at which this jitter occurs is very slow. Due to the fact that the occurrence is at a low rate the overall effect is to have stage 2 tracking on the error of the signal of stage 1, stage 3 tracking on the errors of stage 1 and 2 and finally the last stage tracking on the accumulated (additive) errors of all of the preceding stages.
The third view shown in figure 5 shows a cycle to cycle or adjacent cycle tracking view.
Figure 4. Like PLL's in series (Phase Offset View).
The vertical scale of the plots is frequency and the horizontal scale is time. The plot is composed of hundreds of vertical lines. Each line represents the variation, in frequency, between two successively occurring cycles of the devices output waveform. The maximum peak and valley of the displays indicate the total magnitude of the output frequencies movement of over a thousand cycles while the individual vertical lines represent the very short term (cycle to cycle) movement in frequency. As you can see, the overall medium term wander (maximum height and minimum high points) over a thousand cycles in the displays grows as the signal progresses through the chain (left to right). This is the period jitter that was shown to pass through each stage and get amplified (and accumulate) in figure 3.
Also of very important note is the maximum cycle to cycle jitter numbers shown at the bottom of the graphs in figure 5. What these numbers indicate is that the high frequency domain cycle-to-cycle jitter of the clock does accumulate from stage to stage and its growth is very small. In some systems it will even shrink as it passes through some stages. The reason for this is that Cycle to cycle jitter occurs between adjacent cycles of the clock. In this example the clocks fundamental frequency of the clock is 106.25 MHz. For the waveform to respond to an impulse noise (short period and high in spectral frequency content) it would have to be above 100 MHz in frequency. Otherwise it would (the effect would be) spread out over many cycles. Because this device has a relatively narrow loop bandwidth, this sort of energy is filtered by the skirts of the bandpass curve and therefore does not propagate easily from stage to stage. In well-designed systems, wide bandwidth components can be used to pass such modulation artifacts as a desirable EMI reducing spread spectrum modulation (which occurs at cyclical rates below 35 kHz). Then, to reduce the accumulated high frequency jitter of the system, a very narrow bandwidth PLL device may be used to effectively strip off or filter this and any other high frequency noise before applying the target system devices.
So, let's look at what have we shown by this example. First off, low frequency noise (that inside the bandpass characteristic of a PLL based device) will propagate, be amplified and accumulate as succeeding PLL based clock prosecuting stages are encountered by the signal. If you are designing a system that requires a very long but not short term stable time base (clock) and it is not adversely effected by being instantaneously off frequency, then stacking PLL clock processing devices in series will have minimally affect the system. Because of the very long term Gaussian balanced any short-term period variations are averaged out. Remember per figure 4 the distribution is Gaussian so over a long period of time the average gain and loss are nullified and averaged. The technical term is integrated. The instantaneous frequency at any time, however, will vary over the range that the system will permit it to range.
Thus, if you have events in the system that are very closely timed by two or three successive clocks this is not an issue because this long term period jitter will take too long to accumulate enough error to effect the adjacent clock occurring events. Typical to these applications are the clocking of dynamic memories and the CPU and other devices they transfer data too and from. Here the stability of 3 successive clocks in a RAS-CAS-READ cycle, for instant, are very critical but the long-term period variations 1000 cycles apart have little or no effect.
On the other edge of the spectrum we have seen that the very fast (well out of the bandwidth of the PLLs used in the parts) jitter does not pass through the system of multiple PLL based clock devices. For the most part the cycle-to-cycle jitter present at the output of any device is little more that to the device being measured itself. This means that devices that are very sensitive to changes in the period/frequency of adjacent or very close cycles of their clocks can be expected to work very well with series connected PLL based clock device trees. The main downside impact to applications using series PLL based clock device trees is seen in certain data applications where an incoming data stream has many successive data bits partitioned into very specific and discrete time windows. In this sort of an applications the long term period movement of a clock produced by a long PLL based component tree may cause the clocks to fall outside of the desired cell domains in time when recovering data from a stream.