Digital-to-Analog Converter (D/A) designers are challenged with shorter time-to-market constraints, smaller die sizes, and faster clocks. Trying to meet these marketing requirements on high-speed D/A converters can affect overall performance. In order to accomplish the design goals and meet the expectations of the market, a systematic design and layout approach is essential to the success of the project.
The design of the current-steering D/A converter was based upon the specifications and values shown in Table 1. Three different current-steering architectures were considered in terms of their corresponding strengths and weaknesses. Design and simulation strategies need to account for matching and crosstalk. Even though layout is the last step of the development, it should be in focus throughout the design process. Layout plans help improve device performance and reduce time to market schedules. This paper concentrates on design and layout of an 8-bit D/A converter fabricated in a 0.35u CMOS process.
For the majority of communication circuits, the most commonly used high-speed D/A converter is the current-steering architecture. There are three topologies that support current-steering D/A converters: binary weighted, thermometer coded and segmented. Each has its advantages and disadvantages. The binary-weighted D/A architecture is based on each current mirror being binary weighted to represent its corresponding data bit. Since the switching latches are connected directly to the data bits, the number of latches are minimized and there is no decode required. The major advantages of eliminating the decoding logic and limiting the number of latches not only reduces the silicon area, but also decreases the substrate noise from the digital circuits.
However, depending on integral non-linearity (INL) and differential non-linearity (DNL) specifications, matching requirements can become a big issue in this design. As the number of bits increases, so does the difference between the size of transistors in the current mirrors, thus increasing the error due to device mismatches. Therefore this architecture is not guaranteed to be monotonic, and these matching problems can show up as large DNL errors. Another problem arises at major bit boundaries, for glitches occur when a MSB is turning "on" and all the LSBs bits are simultaneously turning "off ". These glitches cause large spurs in the frequency domain thus reducing your SFDR 1.
The thermometer-coded D/A converter reduces the problems found in the binary weighted converter, but adds design complexity. Whereas most of the matching problems in the binary-weighted design were due to the increasing difference in the size of the current mirrors, the thermometer-coded architecture only uses one current mirror, whose size is equivalent to the least significant bit (LSB). This relaxes the matching requirements to be only within 50%, thus guaranteeing monotonicity and simplifying the layout of the current mirrors.
With each latch turning "on" and "off" only 1 LSB of current, the glitches are proportional to the number of latches changing. Since this type of glitch has a linear effect on the system, there is little to no distortion induced, and thus the THD (Total Harmonic Distortion) is low for this architecture. However, the complexity of the decode is greatly amplified as the number of current mirrors and latches are increased to 2n-1, where n is the number of bits. This not only increases the size and complexity of the layout; it also results in more crosstalk and substrate noise.
Although both the binary-weighted and thermometer-coded architectures have many advantages, their disadvantages have performance or layout limitations that can make meeting all the specifications difficult. Since both architectures have strengths in opposite areas, a combination of the two architectures can reduce their weaknesses to result in an enhanced design. This combining and adapting of the binary weighted and thermometer coded architectures provides the basis for the segmented architecture.
Segmented Architecture (shown in Figure 1) partitions some of the data bits into binary weighted and the remaining bits into a thermometer scale. Each data bit section works as an independent D/A converter with its' corresponding pros and cons. However, when the data bits are combined again, the resulting converter can utilize the advantages from each architecture and only minimal disadvantages. The objectives of the segmented architecture are to reduce glitch energy, complexity, and area, while getting the most out of matching in order to increase the degree of linearity. The success of this architecture is based upon correctly dividing the data bits in order to meet the specifications and size requirements. Since this topology has the best potential in meeting the design goals, it will be the architecture considered here.
Figure 1. Segmented Architecture partitions some of the data bits into binary weighted and the remaining bits into a thermometer scale. Each data bit section works as an independent D/A converter.
Analyzing the design
With the time-to-market deadline and the performance as two major opposing factors, it is important to approach this design from the layout perspective. By viewing the design of the D/A converter in this way, the limitations and delays in physical layout can be largely avoided. Therefore the emphasis will be to minimize the matching concerns by designing for layout.
Having chosen the segmented architecture, the first design issue is how to properly segment the data bits. Since matching becomes more critical for the most significant bits (MSBs), the most common topology has the MSBs as thermometer coded and the least significant bits (LSBs) as binary weighted. Given that linearity is not guaranteed by design in a segmented architecture, minimizing the number of binary weighted bits during segmenting should improve linearity. According to Pelgrom et al. 3, matching to within a 0.5 LSB can be achieved with current sources up to 4 times the size of the LSB. With this knowledge of matching and using the design trade-off of size verses performance, a 6+2 architecture makes the most sense.
Current Mirror Cell
Now that the system architecture is in place, the attention will be focused on the D/A current cell. Figure 2 shows a complete current cell that uses a cascoded PMOS current mirror in a differential current-steering configuration. PMOS transistors were used to reduce the crosstalk noise from entering the current mirrors through the substrate. The cascoded configuration was used to make the current mirror be a more stable current source. The cascode design is based upon making the transistor stack's resistance much larger, therefore making the upper PMOS transistor a solid source for current.
Figure 2. Cascoded PMOS transistors in the current mirror reduces crosstalk noise in a differential current-steering configuration.
Keeping the flow of current constant through each cell is very important to the overall performance of the D/A converter. Thus the bias voltages for the two PMOS transistors should keep the transistors in a saturated state. Consequently, small noise on the power supply or either the PMOS-1 or the PMOS-2 gate will have little effect on the amount of current supplied. It is critical that during a switch from Ioutp to Ioutn or vice-versa that the current remains constant.
There are three things that can happen during a switching time; two are due to parasitic capacitance and the other is due to the bond wire inductance. The first potential problem could be the differential transistors reducing the flow of the current to less than the flow of the current mirror. If this drawback only slightly reduces the flow, it causes the current to flow in and out of the parasitic capacitance at the source of the mirror and results in a small sinusoid at the output (as shown in Figure 3). If the flow of current is extremely reduced or shut down, the quick change in current across the bond wire inductor causes a ringing on the internal power supply. The last concern is the gate-drain parasitic capacitance that leaks crosstalk noise into the system during the transition of the gate at the switch 4. The solution to all of these concerns is found in the design of the logic driving the latch.
Figure 3. Parasitic capacitance and bond wire inductance (between point A and ground) reduces the flow of the current through the current mirror and produces a small sinusoid at the output.
The latch that drives the differential switches in Figure 2 needs to ensure that the current is always flowing at full capacity and doesn't cause too much crosstalk. The solution to keeping the current flowing constantly is to have the latch switching-point low, such that both transistors are "on" before the other turns "off". In this state, the current begins flowing into the other side of the differential gate before the other gate begins shutting down the current; thus eliminating the problems caused by the bond wire inductor and the parasitic capacitance at the drain.
One of the simplest ways to reduce the crosstalk leakage through the parasitic capacitor is to change the size of the voltage swing for the driving logic. This can be achieved by restricting the logic from swinging rail-to-rail, and only permitting the logic to transition enough to turn "on' and "off" the switch. By reducing the amplitude in the driving logic, there is an equivalent reduction in the crosstalk. (A summary of the different types of parasitic capacitance and switching effects can be seen in Figure 4.)
Figure 4. With a constant current topology, a reduction in the amplitude in the driving logic results in an equivalent reduction in the crosstalk. This beats the effects of parasitic capacitance on switching.
With the two LSBs being binary-weighted, the decode is done directly by connecting the two lowest data bits to the low-crossing latch. A popular way to decode the upper six thermometer coded data bits (63 current mirrors) is to place them in a matrix and use a row/column selection method 165. The matrix method is used since the physical matching is best achieved by keeping the current mirrors close and surrounding them by similar cells 3. Since the current mirrors are arrayed, the row/column decode is also one of the simplest methods.
Assembly of the top-level schematic can now begin since all the design pieces are together. Keeping layout in mind, and realizing that the decode logic can be done by a place-and-route tool, it is best to separate the digital and analog portions of the design at the top level. The reason for this separation will become more evident in the layout section of this paper.
In order to keep simulation time down, only the decoding logic, the low-crossing latch and a few different switching scenarios need to be checked. Initially the digital logic needs to be checked to ensure the decode on the D/A converter works properly. Next, several process corners should be processed on the current cell and the low-crossing latch. It is important to make certain that the crossing point and termination levels for the latch do not limit or accidentally leak current through the switches. To reduce the risk of an invalid or leaking switch, the following are a few suggestions for simulations:
First, check the crossing point of the latch at all process corners while including the min, max, and typical temperatures. With the digital inputs set to all zeros, count up to four and check the differential output at each step. Looking at the change in current on both the Ioutp and Ioutn outputs as the D/A converter counts up, provides an idea of how well the latch and current mirrors are working at the extreme output voltages. The next concern is when both outputs are around mid-scale voltage, for it is important to make sure the current mirrors are still able to provide an accurate amount of current to the outputs. Starting the D/A converter at 10000000b and counting up to 10000100b should accomplish this test. When the previous simulations have been completed, a final simulation that cycles through all the data bits can be used to check for any INL or DNL problems.
Cell layout an issue
Up-front preparations such as: digital/analog separation at the top-level, matrix current cell organization and row/column decode should reduce the time in layout by aiding the floor planning process.
Layout floor planning is the best way for an engineer to convey his/her ideas, concerns and design requirements to the layout designer. Knowing the importance of matching the current mirrors, the layout designer should first place the binary-weighted current cells in the thermometer-coded matrix. Then surround the matrix by a row and column of "dummy" mirrors to increase the core symmetry. At this time, the design engineer should also communicate the need for isolation between the current mirrors and the digital circuitry. By using careful isolation techniques such as guard-bars, separate power-supplies and physical cell separation, the layout designer can reduce the risk of digital noise from interfering with the performance of the D/A converter. This floor planning should save time by reducing the number of changes needed in layout and increase the chance of success by isolating the noise and improving the matching.
In addition to the precautions mentioned above, the performance of the D/A converter could also benefit by randomizing the current cells in the matrix. This layout technique of randomization reduces the systematic mismatches due to cross-wafer skews, and has been shown to improve INL 1. Since the digital logic is separate from the analog, this randomization can take place either within the matrix or at the latches.
To reduce time in layout, the placement and/or randomization of the current cells within the matrix could be done using programmable layout cells (p-cells). These p-cells convey the design and connectivity information from the schematic to the layout by automatically creating the physical cell. Once in layout these cells can be moved, oriented or altered in an automated fashion. By programming these p-cells and using a random number generator to label the current mirrors, time can be saved in the analog portion of layout.
Once the analog portion of the D/A converter is laid out, either a shape based router or a place-and-route tool could be used to combine the digital with the analog. By letting the tool place the digital in areas surrounding the analog, unused silicon area can be utilized automatically. After all the individual cells are in place, either tool can be used to route the interconnect within and between the digital and analog blocks. A nice feature of these routing tools is that the layout designer can control each route to be automatic, hand routed or a combination of both. These features provide the freedom needed by the layout designer to control crucial routes and protect "keep-out areas". These tools also allow the engineer to review the placement and routing of the cells and if necessary make changes easily to finalize the layout.
With the use of these automated layout tools, a custom layout can be done quickly without sacrificing performance. The layout of the 8-bit D/A converter (shown in Figure 5) was in a 0.55mm x 0.55mm area.
Figure 5. By using current-steering techniques to weigh bits, the layout of the 8-bit D/A converter is a compact a 0.55mm x 0.55mm cell.
*A version of this article was prepared for the 2000 Analog and Mixed-Signal Applications Conference, and appeared on PlanetAnalog.com
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