High performance clock buffers - those without phase-locked loops (PLLs) - are often used in communications designs for duplication, distribution and fanout of clock signals. Sensitivity to long-term jitter is a critical concern in these applications. Errors resulting from the accumulation of jitter will severely degrade system performance and reliability. While very much less sensitive than a PLL-based buffer, these devices do have a specific contribution of short term jitter (measured as cycle-to-cycle jitter). There is an additional error, with respect to the input reference, from propagation delay and output skew.
Because these buffers are usually deployed for high speed serial communications, designers must optimize system environments such as power supply, input and output transition times, power supply requirements, and board layout in order to minimize these type of effects, and maximize the timing budget allotted. Non-PLL based clock buffers can make a big difference in two areas: One is in clock distribution networks; the other is in differential signaling lines.
Accumulated jitter has its most profound effects where a single clock signal is distributed and fans out of to many duplicate signals. These will vary from the output clocks of the input reference, and as well as from each other. The outputs may 1:1 relationship to the input reference frequency, or dividers may be employed to provide 1/2x, and 1/4x outputs. For purposes of this discussion, high performance translates into high frequency (greater than 100MHz), and implies high accuracy in terms of additive jitter (typically less than 10pS). Phase errors associated with input to output delay (the Tpd) is less than 1 nS, and output to output skew (Tsk) is typically about 150pS.
Figure 1: Examples of Non PLL Based Buffers used for distribution and fanout of clock signals - Circuits shown include a 1:10 non inverting fanout buffer with a divider for the second bank , a basic 1:4 fanout with Tri-state outputs , and a more complex circuit with one of two selectable inputs ( LVCMOS or LVPECL in this example ).
Fundamental knowledge of the requirements of each branch of a given clock tree design is critical to understanding which type of device will perform well in your design/application. Specifically, a detailed understanding of the frequency requirements of each leg of each branch, phase relationships along each leg of each branch with respect to the reference (and each other), and accuracy requirements for both the short term (cycle to cycle), and long term (accumulated over n cycles). Actual load and termination of the transmission line(s) are also crucial to preserving waveform integrity.
An example of how this understanding is applied can be seen in a clock tree design that develops clocks for both control and for the data path. In terms of control, the clock must deliver stable frequency within some ppm spec, and very low short-term jitter in order to guarantee setup and hold timing budgets for what is essentially, a register-to-register transfer. The data path clocks must have BOTH short-term accuracy, and long term stability. ALL clock generators are capable, at some point, of generating a pulse (or series of pulses) that violates the minimum pulse width spec. This will produce an abrupt and short-term shift of phase and frequency, measured as drift for downstream PLL based devices, and potential phase errors for downstream non-PLL based buffers. For PLL based Zero delay buffers, we average this specification as accumulated jitter, where accumulated means over more than two consecutive cycles.
Many designs are sensitive to short term pulse width variations. If the design is using a double edge clocking scheme, then duty cycle, and half period stability (jitter) comes into the picture as well. But the data path has a different need for stability in frequency and accuracy (its tighter, for example, than memory and control paths). Data path specifications reflect long term accuracies, measured as the accumulated jitter specification -- where the length of accumulation is referenced against a number of cycles (10,000 cycles typical).
For short-term requirements, the transfer is complete from one cycle to the other (for example, a register to register transfer). In the data path transfers, it is BOTH short term and accumulated error that is of concern. One issue is drift due to accumulated errors that combine to effect downstream PLLs. These devices may also track high level of input jitter based upon Bandwidth and frequency response, as well as a short-term jitter related to setup and hold times required by downstream devices. In other words, the data path registers both the jitter from the signal itself and from accumulations within its own timing chain.
Non-PLL Based buffers are less sensitive to changes in DC environments than a PLL based device, but as noted, they do offer a measurable error contribution (Jitter, Propagation Delay, Output Skew, and Maximum Frequency). Based on I/O matching requirements (ASIC, Memory, CPU, Chip Set). Concerns about coupling of power supply related transients can effect performance and accuracies -- Power supply switching modulation, Simultaneous Switching of on board circuits -- memory, ASICs, etc.), and load (transmission line balancing, cross coupling/ cross talk, and termination) -- combine to the overall error contribution and input sensitivity of the buffer. Like other PLL based devices, the input signal quality does matter. They ARE affected by input slew rates, duty cycle, voltage swing, common-mode rejection, etc.
The differential signaling lines are similarly by these issues, and designers must make choices based on specific application requirements. Differential signal standards, for instance, offer immediate relief from common mode problems and run at lower power levels. Differential I/O provides higher common mode rejection, faster speed (due to smaller voltage swings), and lower power consumption. There are several differential I/O specs, but the three that are most popular are LVPECL (Low Voltage Positive Emitter Coupled Logic), LVDS (Low Voltage Differential Signaling), and HSTL (High Speed Transistor Logic).
Figure 2: On differential lines, the dc steady point (VTT) is determined by the balance of two drivers. Buffers can simplify the termination and filter requirements.
Buffers may ease some of the termination requirements for differential signaling, but not in all cases: A backplane application, for example, requires termination resistors on both ends of the coax cable -- 330 ohm resistors are just before the backplane, 50-ohm resistors are at the input of the receiver. The 330-ohm resistors are used to provide a stable noise environment in the event that the card containing the receiver is pulled.
With differential signaling point-to-point, the 330-ohm resistors are removed to save components, space, and cost. The standard 50-ohm resistors to VTT are still used since LVPECL (used to drive point-to-point) is an open source. That is, the 50-ohm resistor to VTT serves as the voltage load (VOL) on the driver. Without this connection, a poor waveform might be seen at the receiver device. Some PECL and LVPECL implementations have totem-pole like output drivers, but these are not in the spirit of ECL, or took the pseudo to heart. The driver waveform may be slightly different since the loading effect has been altered, (from the 330's, backplane connections, and transmission lines), but is designed to be used in this mode.
There are also devices that contain an internal termination (ODT -- on die term) on their inputs so the interconnect is easiest. Waveforms may differ between devices since process variables can change this termination.
There is often noise present on the central point between the two resistors. On differential lines, the dc steady point is determined by the balance of the two drivers. Once VTT is provided, this drives this level. Above this DC level is VOCpp and is defined as "Driver common-mode p-p" and is the summation of the output driver and the environmental effects from the driver to the receiver. Often this is induced by the PCB design. In any case, a capacitor or RC filter - a jitter filter - will block out this unwanted noise.
Deterministic Jitter, causing the unwanted waveform distortion or oscillation that can occur from outside interference or internal, (e.g. the IC design, environment, or PCB) design feature that generates a waveform other than that is wanted. Where does it come from? Two sources mentioned earlier are power supply and layout. High speed isn't as easy as the high speed of yesterday! Layouts, more than ever, affect waveform integrity. In the case of "high speed", ground planes rule. Grounding schemes are a very important quantity in design. Actually all of us know this, but a few reminders will help. Under high speed clock devices, in general, provide a pool of ground. Watch for potential ground loops, and isolate Digital and Analog grounds where possible, tied at a single common point close to/under the device. This has been found on various designs from RF to high speed digital to reduce noise within an IC.
With differential traces, the capacitor or RC filter is a required element when the traces are not of equal length and when they aren't laid out in parallel lines from the driver to the next receiver. Why parallel lines of close to the same length? Besides the obvious issue of length equality for skew issues, other issues include radio-interference or simply radiation from close lines or other on board devices. If both lines see the same signal, then the differential form will subtract one lines value from the other lines value -- resulting in a net offset of zero. If one trace is out of order (as with bad termination) or is influenced by an adjacent trace, the difference between differential trace signals shows up as interference. Noise or jitter of this sort can be additive between stages, and a small value builds as the number of stages increase. It is best to start with a clean signal whenever possible. Internal logic may turn on, or maybe not turn on, due to noise riding on the circuit.
How to measure the jitter component of a specific stage of a clock tree or simple buffer is defined in a parameter of delay. Most digital oscilloscopes have a one-shot measurement capability that is capable of capturing jitter. Most, if not all, now have drivers that use external software that calculates jitter components. The Deterministic Jitter can be measured by use of Jitter of Tpd. Propagation delay jitter (also know as I/O Jitter measurements), subtracts out the input jitter component as one measures from the input pins to a given output and that value is subtracted from the delay measurement probes.
Theoretically, no jitter is derived at the output pins (that is, in the propagation delay number), some value derived from subtracting the propagation delay from the measured value leaves deterministic jitter. Measure the jitter, run a Fast Fourier Transform (FFT) on the jitter to identify frequencies of that jitter, and apply a small filter - maybe a simple capacitor - and re-test. Trial and error often yields respectable results. Loop back until the job done. #