Designing a high-speed digital backplane requires a great deal of attention to both analog and digital design. As signal highs and lows change state, designers are challenged with issues such as signal integrity, edge rates, and timing. However, power management and configuration are issues that are critical for a high performance backplane. What follows is an analysis of a backplane utilizing Gunning Transceiver Logic Plus (GTLP) from a power perspective. Each independent voltage level has different needs both in terms of energy usage and more importantly, noise characteristics. This paper will provide valuable information on the appropriate power requirements for a GTLP backplane.
Backplanes can be broken down into discrete live insertion capability levels. These levels and hardware requirements for each are discussed in the live insertion section. Implementing the recommended Power Up sequence will result in uninterrupted data on a parallel backplane without the need to halt data transmissions.GTLP Definition
GTLP is a single-ended, open-drain backplane transceiver technology for high-performance buses. As a high-speed, high-drive technology, GTLP enables extended backplane performance and provides increased throughput in heavily loaded environments.
Incident wave switching enables higher throughput
Reduced swing, tight threshold, and controlled edge rates for low noise and EMI
User ability to adjust variables (RT, VT, and VREF) to optimize backplane characteristics
Live insertion capability
Interfaces TTL to GTLP
The most common area in which GTLP devices are used is telecommunication. The backplanes are typically multi-drop wired, giving each card the ability to communicate with every other card. Moderate to heavily loaded backplanes using GTLP see operating frequencies that range from 33MHz to 100MHz. These systems provide throughput capacities in excess of 10Gbps, depending on the width of the system.
Power Configurations Analysis
<>Device Bias VCC
Datasheet specifications list this level as ranging from 3.15V to 3.45V, a variance of almost +/- 5%. In order to meet all data sheet performance specifications, this condition of voltage range must be met. Maintaining a level in this range is a relatively simple process and often generated by a master supply, possibly a switching or linear regulator, in the backplane cage. The common problem in this process is the distance between the cleanly filtered master supply output and the GTLP device that it is powering. It is in the distance range that a problem is oftentimes encountered.
When troubleshooting a device, it is imperative that the VCC oscilloscope probe and ground be placed as close to the device as possible. It is here that disturbances are seen. Putting the device through the various configurations possible during operation is also important. Clocking data in the AB direction while under Multiple Outputs Switching (MOS) is perhaps a worse case condition, but this can vary between applications. It can also be just as beneficial to monitor the ground plane for noise. There is often more than one VCC pin on a GTLP device that provides better power distribution inside the device. Each of these will be wired to the VCC plane of the PCB, but each should also have its own bypass and or decoupling capacitors as close as possible to the device. Depending on the size and frequency of the disturbance, more than one size and type of capacitor may be required.
How much noise is acceptable? Of the three voltage levels that GTLP devices require, VCC has the greatest amount of tolerance. However, a spike of relative magnitude can be seen on the device outputs, often evident in the edge rate integrity. It is at this point that great noise reduction measures should be taken. This could include a local voltage regulator.
Termination Voltage (VT) Introduction
Due to the open drain technology used in GTLP output buffers, a pull up level known as VT, nominally 1.5V, is required. When a GTLP device receives a high on the TTL input, it simply turns the output buffer off allowing the voltage level of the trace (labeled as VOH in datasheets) to be equal to the termination voltage.
Since the level of VT directly affects the VOH level, there are advantages to adjusting VT. Observations to be made during VT adjustment include:
1. Noise Margin Associated With VREF
When VREF adjustment is not available similar results can be accomplished by adjusting VT.
2. Power Consumption
As VT is increased, the current through the device in a low state, IOL, will increase. This increase may be a concern if minimizing power is a priority. The obvious trade off to lowering VT, and hence, lowering power consumption is possible noise margin violations.
It isn't until a low bit is received that the connection is made between the termination voltage and ground. The effective low on the bus, labeled as VOL in datasheets, is then the factor of a voltage division between the termination resistance RT and the on resistance of the GTLP device RDSON. The figure below illustrates this:
Figure 1. GTLP output buffer showing device RDSON.
Devices with higher drive, 100mA versus 50mA, have a lower RDSON. Therefore, this VOL calculation can vary between devices. It can also vary considerably with temperature. Each GTLP device has its own VOL vs IOL plot across temperature that can be used to calculate this RDSON. It is important to note that two devices from separate manufacturers capable of driving 100mA do not necessarily have the same RDSON as there may be slight design differences. Always consult the datasheet or extended characterization for specific values. Typical values for RDSON are in the 3-ohm range for 100mA drive devices and 6-ohm for 50mA devices. Device temperature has the largest impact on this value. As the package temperature increases, the resistance will increase, hence decreasing the drive capability of the device.
A common question regarding open drain technologies is: what is required of the voltage source VT and what are possible configurations for it? It is evident that large amounts of current can be demanded from VT based on the number of bits switching on the backplane and the value of RT. But keep in mind that since the level of VT sets VOH, any drops in the voltage level of VT will result in a degradation of the upper noise margin, (the distance between VOH and VREF).
Current spikes are also experienced by the termination supply. The two major factors that affect the value of this spike are inductance (L) in the transmission line and the rate at which the current is changing with respect to time (dI/dt). A Time Domain Reflectometry (TDR) device can be used to measure the amount of inductance associated with a given trace. It can also show the location of the inductance. The figure below shows the current measured at the output of one of two VT regulators (one regulator is at each end of the backplane) while 3 bits are toggling at a slow rate in a GTLP16T1655. Because of the type of probe used, the DC current level that the signal settles to is not correct. These small spikes should be considered when calculating power ratings for supply components.
Figure 2. Current spikes on VT when 3 bits are simultaneously low..
VT Power Consumption
As previously state, each bit switching in a GTLP device contributes to the power required from the VT source. The figure below shows the linear increase in current as a series of bits are pulled low.
Figure 3. Outputs switching versus termination supply current.
Linear Regulator VT
One approach to generating a fixed termination level is to use a voltage regulator such as the Fairchild Semiconductor RC1585. This device is a 5A adjustable/fixed low dropout linear regulator designed specifically for GTLP use. With an input voltage of 5V or less, the RC1585 offers a regulated output range of 1.5V to 3.6V. Regulators are known for their ability to source relatively high amounts of current given their size. The RC1585 circuit, when properly design into an application, can handle microsecond surge currents of 50A to 100A. These regulators also have the ability to sink fair amounts of heat based on their physical size and structure. One disadvantage of this robust device is power efficiency. Depending on the make and model of a linear regulator and the application at hand, it is possible to see relatively low efficiency. With such a range for input and output power ratings, the benefits of linear regulators are often good tradeoffs for efficiency. The solid regulator output coupled with a storage cap for tough to manage loads is a commonly used and effective solution.
Regardless of the regulator chosen, this method still requires a capable master supply for its input. Let us say that a single regulator was used as a VT source and provided the desired output at 60% efficiency. If one 100mA drive device were in operation and all 16 bits were held low at maximum current (i.e. RT and VT is set such that 100mA is traveling through each output buffer), the total power required from VT is 1.6A. At 1.5V, the required output power of the linear regulator is 2.4W. Operating at 60% efficiency, this equates to 4W required from the master supply.
Figure 4. GTLP termination circuit using a linear regulator
Thevenin Equivalent VT
As PCB real estate decreases, it is occasionally not feasible to use a voltage regulator for VT. Another option is to use voltage divider circuits off the VCC supply. If done correctly, this can be a low cost solution to any design. Since the circuit is tied directly to the master VCC source, all noise and transients will be evident on VT. Precautions such as appropriate decoupling and resistor power ratings must be made close to each 1.5V node.
The major concern with this method is determining exactly how much resistance (RT) is seen by each trace and what is the associated pull up voltage level after properly considering all voltage drops. With GTLP backplane designs, a termination resistor variation of even 5 ohm can be easily spotted in the signal's shape.
Figure 5. Representation of Thevenin equivalent circuit for GTLP termination
A simple divider from 3.3V down to 1.5V is not the complete solution. All resistances must be considered simultaneously. One resistance that cannot be changed is internal to the device : RDSON. The drive of the device dictates this value, ranging from 3 ohm to 6 ohm for 100mA to 50mA drive, respectively. Since R1 in parallel with R2 is the Thevenin equivalent termination resistor, selecting resistors so that the parallel combination matches the effective impedance of the backplane and produces the correct voltage levels can be difficult. The figure above is a general representation of the complete circuit when a low bit is on the transmission line and RDSON is seen.
When a high bit is on the transmission line, the VT node only has the high impedance input of the receiver to contend with. At this time, 1.5V is required from the node. It is for this reason that each transmission line requires a separate Thevenin termination. If two transmission lines were connected to the same VT node and one bit was low while the other was high, there would be contention. Therefore, while this Thevenin approach is somewhat less complicated than the linear regular method some tradeoffs are made. Resistors are less costly than a regulator but an additional 128 individual resistors would be required for a 64-bit backplane if Thevenin were used instead of a regulator with RT.
After considering appropriate resistor values and power ratings, what other concerns exist? As with all voltage dividers, a constant path to ground is provided. Therefore, power is constantly dissipated through the resistor combination. Considering this during the Thevenin circuit design, power consumption can be minimized during the resistor selection process. The result can be an effective power supply design that may be more cost effective to produce.
Keep in mind that the Thevenin method consumes twice the power of an "ideal" linear regulator method. The efficiency of the regulator, which varies between applications, will be the deciding factor. Opting for a VT supply with higher efficiency, such as a fly-back switching supply, would be another consideration, although this option is quite costly. If a designer is searching for a method to isolate noise on VCC from the VT node, both methods with their bypass capacitors will provide the same level of isolation.
The question might be asked, how does one know when the VT source is to blame for signal integrity issues? This is a difficult task since RT selection is often the largest culprit relating to signal integrity problems. The first obvious sign of an inadequate termination is GTLP signals not reaching the proper VOH level of 1.5V. Yes, Rt can be at fault here but if one wants to isolate the problem down to the termination supply, adjust the operating frequency to a very low rate. At 1MHz, a signal not reaching VOH is more than likely due to the improper resister if a Thevenin application is used or otherwise, it may be attributed to current limiting. Note what other events may be simultaneously occurring as well. The transmission of a word consisting of 16 Lows on the same bus but through a different device may be where all the power is distributed. If a required power level cannot be met by a supply it will sacrifice voltage levels to meet current demands. Pay attention to current specifications on supplies and note at what voltage they are specified at.
Insufficient capacitor selection for VT can also affect signal integrity. This compromised signal integrity can be discerned on the falling edge of GTLP signals when current is sourced from the termination supply. Adjusting the value of the capacitor(s) on the supply will result in minor edge rate changes and even effect VOL and VOH levels. After calculating one capacitor or set of capacitors, venture to each side of the spectrum and observe the results in signal integrity. Parasitics and underestimated surge currents can exceed the variables used in calculations.
Variable threshold voltage VREF
Capable of adjusting the threshold level at which a GTLP edge results in a TTL edge when operating in the BA direction, VREF has the smallest power requirement of the various GTLP voltage levels. Requiring less than 1mA, a simple voltage divider circuit is recommended. Sizing the resistors accordingly for this consistent, small current will limit the amount of power constantly drawn to ground. There is a tradeoff between power and noise immunity. Although larger value resistors will require less power, lower impedances will better dampen noise spikes. Using a linear regulator for VREF would be functional but it is over design. Although VREF requires such a small current, do not underestimate the importance of the voltage.
Datasheet specifications recommend +/- 2% control on this nominally 1V source. Any shifts on this voltage level at the input pin to the GTLP device can introduce unwanted skew and possibly cause false glitches if the shifts are excessive. Sufficient bypass capacitors placed near the device on the VREF line can help a great deal in eliminating false glitches. Since adjusting VREF can improve noise margin and TTL output duty cycle, it is common practice to implement a potentiometer for minor tweaking in an engineering model. High accuracy discrete resistors are typically used in the final model. If any transceiver is dedicated as a driver only, it is not necessary to connect the VREF pin to the 1V supply. A connection to ground will suffice for this application. The VREF pin is only required for the receiving function of GTLP devices.
While adjusting VREF one should focus on the following parameters:
1. TTL Output Duty Cycle
On a non-inverting GTLP device, TTL output duty cycle will increase as the VREF level is decreased. Select a level that provides the optimum duty cycle for system timing.
2. Signal Integrity
While adjusting VREF will not improve the shape of signal edges, it can be adjusted to shift the threshold level above or below particularly degraded sections. If the GTLP signal passed through the threshold region twice, i.e. fell below 1V and experienced a slight reflection bringing the signal back up to 1.01V then continuing to fall, a glitch would be evident in the TTL output. A minor VREF adjustment to 1.05V could be a simple fix.
3. Noise Margin Associated With VREF
Adjust VREF such that upper and lower noise margin, i.e., the distance from VREF to VOH and VOL, are equal. This adjustment better prepares the bus for an unanticipated EMI or noise event.
After adjusting VREF, it is important to observe the changes in all possible configurations so that the backplane can eliminate undesired side effects. Difficulty can sometimes arise when VREF conflicts occur between options. VREF is typically set at one level but adjusting it through a dynamic control that can sense backplane loading during operation is possible.
Referenced several times above is capacitor selection. Various types and configurations are available and necessary in all backplane designs. In any application, they are used to apply control through filtering or as local energy storage devices. On the power legs, such as VCC, the bypass capacitor is used to maintain a set voltage bias for the device during current transients. While current transients are not high on the VCC pins, the voltage they condition is crucial to operation of the chip. A drop below 3V for most 3.3V devices degrades the delays for the device to specifications outside those guaranteed in the datasheet. Capacitors selected to protect a voltage drop of 300mV are not the only decoupling to be considered. High frequency noise on the VCC line should also be filtered as best as possible.
The largest current transients on any GTLP backplane will occur at the VT node, as discussed earlier. Here, there is no crucial level that must be maintained. Each application will have different noise margin requirements that dictate the VT level. It is common to maintain VT within 100mV, since noise margins are often greater then 200mV.
In either of these cases, to include VREF decoupling, selecting the value and number of capacitors is an art that varies between applications. Items to consider include: supply impedance, voltage delta allowable, trace size, lead inductance, equivalent series resistance, resonant frequency, etc. Cookbook equations can be used as a starting point but text references should be consulted prior to final design. The purpose of this paper is to present the various power requirements and configurations of a backplane, which will aide in the selection of decoupling capacitors.
Power Level Summary
Several specific voltage levels require attention when designing with GTLP. Although each level has its own set of requirements these voltage levels can each be derived from one master supply, simplifying design and reducing cost.
Having the ability to set the level of these required GTLP voltages is an added bonus to any design. Keeping the datasheet specifications in mind, adjust VREF and VT through their recommended ranges and observe the effects on the signals. This offers the designer the opportunity to create a robust and custom backplane with superior performance in the application at hand.
Live Insertion Introduction
As backplanes grow in size, turning them off to remove or insert a line card is becoming more a concern. What follows is a technical discussion on design considerations in such an application where live card insertion and removal is required, also known as hot swap. The various stages of live insertion will be presented followed by physical hardware considerations, such as pin lengths, followed by an evaluation of VCC BIAS, also knows as output pre-charge. Lab data from Fairchild Semiconductor's Ensigna Lab will point out advantages and disadvantages of the options available to the designer.
Live Insertion Levels
Systems are typically characterized into discrete live insertion levels based on the systems requirements for a card insertion. These requirements can be broken down into three levels:
Level "0" Isolation
Live insertion is not possible with a device that falls into this category. Due to the device characteristics the backplane and host system would have to be powered down completely to insert a card.
Level "1" Isolation
This is defined as the ability of an interface device to allow insertion of a board into a backplane without powering the host system down.
Level "2" Isolation
This is defined as the ability of an interface device to allow insertion of a board into a backplane without powering the host system down or suspending active backplane signaling.
GTLP devices are categorized into both level 1 and level 2 isolation, depending on the design of the system they are in. With no pin sequencing on card insertion, a glitch can be seen on a backplane signal at the point of insertion. This situation would put GTLP into level 1 isolation requiring all transmissions on the backplane to cease prior to card insertion. However, if during the insertion the device is powered up using the correct sequence of events, data traveling on the backplane is not affected. Pin staggering, and possibly VCC BIAS, is required to achieve this highest level of isolation.
In order to minimize the effects an inserted card has on live data switching on a backplane, pin staggering should be adopted. Dealing with the input capacitance of the GTLP output is the primary concern. It is the charging of this capacitance that can cause a glitch on the signals present on the backplane. Staggering the card connector pins on a card without VCC BIAS is as follows:
1. GND -- establishing the ground connection first provides a path to ground for any unwanted charges that may exist on the card prior to insertion.
2. I/O Data -- connecting data lines second will ensure that I/O pins are high impedance
3. VCC -- leaving VCC for the final connection (shortest pin) eliminates the chance of any outputs having a charge prior to insertion.
In the event that pin staggering alone results in bus contention on live insertion, VCC BIAS is a device feature that addresses this problem. This essentially pre-charges the GTLP outputs on the B port to a solid 1V level when voltage is applied to the VCC BIAS pin on the device. Both the VCC BIAS and GND pins must be connected first in order to properly charge the outputs. After the device has power asserted to its VCC pins, the VCC BIAS pre-charge is removed from the B port output pins. This is why the VCC pins must be last to receive power.
Regardless of the type of pin staggering used (if any) it is very important that the GTLP device being inserted be in high impedance mode, i.e., /OE pins tied high. Inserting the device with either /OEAB or /OEBA directional pins enabled will result in bus contention. Immediately following insertion, the device outputs may be enabled by toggling /OE pins to a low state.
Do You Need Vcc Bias?
The Fairchild Semiconductor EnSignaTM Lab conducted a study to evaluate and observe the performance of VCC BIAS in a 21-slot backplane. The backplane was configured with a driver in Slot 18 and a receiver in Slot 13 while the remaining slots were left open. Specifications for the backplane include:
VT = 1.5V
RT = 35 ohms
VREF = 1V
VCC = 3.3V
Pins on the cPCI connectors were staggered to power the inserted card in the order of VCC BIAS and GND, then I/O pins, followed by VCC. The driver and receiver were enabled and data was transmitted between the two. A card with GTLP16T1655s set in high impedance mode was then inserted into Slot 10 of the live backplane with an oscilloscope recording various waveforms at 5G samples/second.
The following figure depicts a card inserted in the middle of a high pulse on the backplane. Noticing that the line was initially at 0V, one knows that VCC BIAS was not enabled on the device for this particular scope capture. Channel 2 (TTL output) is unaffected but there is a concern about how close did the system come to losing data? From the plot one can see that 228mV of noise margin still exists between VOH and VREF levels. This exceeds the nominal minimum level of 200mV noise margin, which credits this particular system with being a functional live insertion backplane for the particular card configuration and frequency. The VOH levels return to their original 1.5V level after the VCC pins make contact.
Figure 6. Live insertion event with no VCC BIAS
As shown in Figure 6, a disturbance is noticed on the GTLP signals at the driver and receiver. Although this disturbance is minimal, it is clearly evident. The VCC BIAS option is enabled on the card being inserted in Figure 7. This is evident in the graph since the inserted card is already at the pre-charge level of approximately 1V. The TTL output from the receiver card is still uninterrupted but the noise margin separating the insertion from a false trigger is now 360mV. Looking closer at VOL, one can see that a 200mV spike does exist after the insertion. The inserted device is introducing a 1V potential for several pulses, depending on frequency, after the insertion prior to VCC pins making contact. After the VCC connections are made the pre-charge is eliminated, as well as the spike.
Figure 7. Live insertion event with VCC BIAS enabled
From the results above, it is evident that VCC BIAS does indeed make a difference during live insertion. In this particular system, enabling VCC BIAS may not be a very high priority. However, in a system that is already designed with close noise margins, not having VCC BIAS may put the system in a marginal state resulting in random glitches on the TTL outputs. Therefore, the answer to the question, "do you need VCC BIAS", is completely application specific. Lab data suggests that it is definitely a matter to look into but not necessarily something that should be automatically adopted.
The data presented is simply a collection of two plots. The amplitudes of the spikes and resulting noise margins do vary between insertions. In this particular backplane, these variations were minor so only two plots are shown. A card inserted in an unloaded backplane during a high signal will produce different results than a card inserted in a heavily loaded backplane during a low pulse. Observing live insertion events under different conditions prior to making a final design decision is required.
Another subject often not mentioned around the live insertion topic is power supply drop out. When a card is inserted into the backplane, voltage transients are seen on the VCC pins and traces. It is important to evaluate the condition of these power lines during a hot swap event. Having ample decoupling capacitors at the devices and larger capacitors on the power supply outputs are common methods to assist this overlooked phenomenon. In evaluating the backplane used in the results above, a card insertion did cause a slight drop on the supply lines but no data was corrupted.
Deciding the level of live insertion required for the interface system in its early definition or design phase is essential for a successful hot swap design. Many considerations, such as cost, speed, power, will have to be evaluated but live insertion is not a feature to be simply added to a design in its final stages. If the system control software requires a backplane to be powered down for removal or insertion of a card, there is obviously no reason to implement a staggered pin or VCC BIAS layout. When the proper design techniques are employed, GTLP devices are solid transceivers that can easily perform in a system requiring live insertion capabilities.
Power Management Conclusion
Several topics were addressed concerning power management in backplanes. Three basic voltage levels, VREF, VT, and VCC, are required by GTLP devices and options are available for generating each of them. Adjusting VREF and VT, is encouraged. These levels oftentimes are set to the recommended level and remain unchanged throughout the design process. The tradeoffs associated with these adjustments were listed and can be applied as necessary to various custom backplanes. On a different end of the power spectrum, a generalized comparison was made between backplanes with and without the VCC BIAS option enabled. The conclusion was that this option may not be necessary and should be evaluated for the system in question prior to consuming unnecessary resources. Three discrete levels of live insertion, 0, 1, and 2, were also listed and can be applied to numerous backplane technologies, to include GTLP.
If a designer keeps these power issues in mind in the early phases of backplane design, the result will be a more robust backplane that provides increased system performance.
*This is a version of Eddie Suckow's DesignCon 2002 High-Performance System Design Conference presentation. The online version of this article also explores the topic of live insertion in backplanes. Design requirements such as pin staggering and expected power transients are shown. Steps to achieve live insertion and the results of this live insertion process are discussed. This live insertion section includes a study on the pre-charge option known as VCC BIAS. VCC BIAS is often times considered a must have in backplane designs. Lab plots show device performance in a backplane both with and without the function enabled.