Technology's relentless march toward ever increasing CPU speed and performance is taxing today's power systems and promises to demand significantly more in the future. While processor core voltages will drop to 1 V and below, current demand will rise, likely topping 150A by 2005. Simultaneously, processor clock frequencies will push into the multiple-GHz range, yielding transients estimated to be 1000 A/ns at the processor and 1000 A/us at the socket. At these rates, even the smallest parasitic inductance creates voltage transients that can overwhelm sub-1V logic gates. Current technology has been shown to generate 160 mV voltage transients on a 1.5 VDC core voltage, a variation that threatens data integrity.
This article explains and promotes Digital Multiphase Power (DMP), jointly developed by Primarion and Intersil. This is a scalable architecture that offers a very fast and stable response to current surges.
Today's processors are powered by multiphase, buck switching-converters that consist of a switching controller, gate drivers, and discrete FET power stages. To minimize line inductance, OEMs place the core power supply at the processor, but this requires the supply to conform to a very small form factor - and to be very high efficiency in order to minimize heat. By putting MOSFET drivers in parallel, multiphase buck regulators can provide very high currents, in excess of 60A (Figure 1).
Figure 1 Typical multiphase buck regulator schematic.
The issue is how well do they respond to transient current requirements? To meet the transient requirements of 2GHz and greater processors, a multiphase regulator must actually operate in two modes, normal and Active Transient Response (ATR). In normal mode, phase pulses are evenly distributed across the switching cycle to minimize the combined ripple (as shown) in Figure 2a. This allows for phase inductance values to be lower than a single phase design as the ripple is the sum of the inductor phase ripple currents. But during ATR the phases are timealigned yielding a current ramp that is the sum of all phase ramps, effectively paralleling the inductors (Figure 2b).
Figure 2: In normal operating mode, phase pulses are evenly distributed across the switching cycle to minimize the combined ripple (top). During a transient, a control loop will time-align the MOSFET phases - effectively paralleling the inductors - to make a smooth current ramp (bottom).
When the processor experiences a rapid rise in load current, the inductor current ramp is increased by turning all high side FETs on and aligning the phases. The inductor current ramp rate is now:
- Vin = the input voltage
- N = the number of phases
- L = the phase inductance value
The inductance value in the denominator combined with the number of phases, N, in the numerator results in two factors that enhance current ramping. The benefits of lower inductance values from the multiphase design and high system switching frequency favor the circuit's di/dt ramp rate. (The Digital Power Architecture allows designers to add phases at will to a maximum of N = 8 and choose low inductance values due to the 1 MHz switching frequency.)
DMP optimizes performance in both modes and smoothly manages mode transitions. Rapid and efficient transition from ATR to normal mode requires adjustment of the control loop. Digital control, offered by DMP, provides for such a smooth transition between ATR and normal operating modes. It uses a control loop correction algorithm to manage ATR activity. With this algorithm (for which Primarion has filed a patent application), output settlingtime between modes falls from 50 us to 300 ns.
The Primarion/Intersil DMP architecture is essentially a multiphase buck regulator topology. Its power partitioning integrates the high-side FET with the gate drivers and analog-digital interfacing. This allows control intelligence to be keyed on the integrated high-side FET, while low-side FET flexibility is maintained for addressing dissipation challenges of high step-down ratio, low duty-cycle applications (Figure 3). The architecture allows up to eight phases operating at up to 1 MHz for di/dt rates in excess of 800 A/us at the inductors and over 1500 A/us at the output capacitor.
Figure 3: DMP from Primarion/Intersil changes the controller architecture from typical analog control to digital control with associated signal and power partitioning.
By isolated analog signals at the Driver/FET and using digital signals to communicate with the purely digital controller, the DMP architecture offers potentially greater noise immunity. The signal partitioning offered by digital control allows for better optimization and real-time adaptation of the control loop. The controller also provides a digital link to the outside world - in this case, the host CPU - allowing the user access to programmable control-loop characteristics and readable system status data. The programmable DMP architecture is thus reusable across multiple voltage and current applications and can accommodate future processor needs.
DMP architecture facilitates the implementation of flexibility and scalability features in the regulator design. The multitasking that DMP naturally provides allows quick adaptation of the ATR window to match changes in AVP and VID. DMP automatically supports one to eight phases per controller allowing designs to scale to meet output load current requirements. Also, current is evenly distributed among the phases by the DMP control. Future versions of DMP will detect the loss of a phase and adjust the system accordingly.
Serial digital signaling allows for point-of-load placement of the power stages independent of controller placement. Digital signaling to the power stages confines drive currents to the power stage, along with the analog signals. The integrated design and use of advanced semiconductor processes enables the DMP solution to operate up to 1MHz. This increased switching speed reduces filter component size and maximizes system bandwidth to increase current ramp rates.
The selection of lowside FETs is based on the response time versus efficiency tradeoff. The DMP architecture allows both the switching frequency and dead time to be adjusted for optimal performance with chosen FET and at various system operating conditions.
Design Optimization and Diagnostics Monitoring
Optimizing the power system for the chosen processor load is critical to today's computer system design. The DMP architecture from Primarion /Intersil allows the power system designer to set key performance parameters through the Primarion "PowerCode" Architecture Manager software. This innovative tool allows designers to optimize the power system for the processor it powers. Designers can choose low side FET types, phase inductor values, output capacitor values, non-overlap times, loop compensation, AVP window, voltage and current, fault monitoring indicators, and various support component values. Once these values are inserted into the variable fields, system performance is easily simulated and tested. Data generated by the Primarion PowerCode software can be ported to PSPICE or Matlab simulators for more detailed analysis.
Figure 4: Primarion PowerCode Architecture Manager software allows users to simulated the effect of FET types, inductor and capacitor values on multiphase regulator performance.
Recent processor designs specify the amount and location of the voltage regulator output capacitance, which necessarily impacts the regulator's bandwidth and stability. Via the Primarion PowerCode software interface, the control loop is easily adjusted for optimal performance with the specified capacitance and other system parameters. These adjustments can be made during system operation. Designers need not shut down the system to change analog loop components. These in situ adjustments allow rapid, non-invasive system optimization, a boon to any product development.
The ability to quickly customize designs and optimize system performance also means a reduction in inventory required to adjust systems to specification. Rather than storing an inventory of analog components and perhaps controllers, system customization is reduced to adjusting a set of digital parameters loaded into the controller.
The Digital Multiphase architecture is inherently adaptable to various low-voltage, highcurrent applications such as DDR memory, memory hub controllers, and DSPs, as well as other computing platforms. By matching the power stage components to the application, users can scale the design to optimally meet current and ripple demands. At 1 MHz switching frequency users can add phases in 15 A increments; of course other current and frequency phase combinations are possible. The DMP operating range of 250 KHz to 1 MHz allows system optimization when considering the tradeoffs of response time versus efficiency.
Switching frequency has a direct effect on overall system efficiency. With DMP control, the designer is free to set a slower switching frequency for improved efficiency, or faster switching frequency for rapid response to load transients. By simply inputting new values into the software, switching frequency is easily optimized. Likewise, the DMP architecture allows designers to optimize inductance versus number of phases, which directly affects output ripple voltage and system response.
DMP enables an upgrade path to meet everincreasing microprocessor slew rate requirements. The DMP architecture establishes an Active Voltage Stabilization Interface between the DMP regulator and pointofuse transient regulators residing inside the processor package. This system balances power sourcing between the switching regulator and the transient regulators, minimizing thermal impact to the processor while maximizing system performance.
The future for digital control of power systems is very bright. Control through programming expands the functionality of the controller. Future digital controllers could easily regulate multiple voltage loops, detect loss of phase, and scale to greater than eight phases. Multiple voltage regulation could include a step down front end for the 48V market. All of these options are provided through software programming therefore reducing the amount of added circuitry required to increase functionality.