As operating speeds continue to steadily increase, the performance of packaging interconnects can dominate overall device performance, often in a negative way. Therefore, with increased signal speeds, the chip-to-chip interconnection path (the package) becomes the limiting factor in system performance. Parasitic effects, such as crosstalk, delay, and simultaneous switching, significantly impact overall system performance. To minimize these effects, path lengths must be short, capacitance and inductance must be reduced, and impedances must be controlled to a specified value over a wide bandwidth.
Because of this, accurately simulating the behavior of a package is more important than ever for meeting performance requirements, reducing the number of design-fabrication cycles, and speeding up development time.
Obtaining an accurate simulation of a package that carries high-speed signals begins with a physical description of the package, including layer stacks, trace geometries, and electrical characteristics of the materials that are used. This information is used to perform an electromagnetic simulation of the structure, from which a SPICE netlist is generated. SPICE is then used to verify timing requirements.
According to Leah Miller of LSI Logic, there are three approaches that engineers can employ to design IC packages:
The "board-up" approach: Assumes that a board is already laid out and that a new package is created around this design. While the board is finalized, the package and die must adhere to the pin pattern. This approach is best suited for second sourcing of existing packaged devices.
The "silicon-down" approach: Used when an ASIC design company strictly designs the functionality of the ASIC and uses a packaging vendor to customize a package to fit its design. This approach is well suited for fabless companies and requires a custom package design.
The "off-the-shelf" approach (explored here): Employed when a package that has already been laid out is used as a basis for the die and board designs. The package has probably already been measured and characterized to a certain rise time. So, if signals coming from the die fall within the package's tested capability, the ASIC design company saves time and money since there is no need for customization.
There are many different types of IC packages in use today, including Leadframe, Quad Flat Packs (QFP), Chip Scale Packages (CSPs), and Ball Grid Array (BGA) packages (Figure 1). BGAs, in particular, have become an attractive alternative for high lead counts due to their improved I/O density and better thermal and electrical performance compared to the other styles.
Figure 1: Cut away BGA view illustrating current flow through traces, vias and ground planes
BGAs naturally lend themselves to high-speed applications because of their small values of stray reactance, allowing for minimal signal distortion. The high density and high pin counts of these packages, however, present an additional technical challenge caused by crosstalk between traces. These coupling effects, and other phenomena, have origins in electromagnetics and are, therefore, accurately simulated with an electromagnetic-field solver.
To minimize the overall design process time, it is increasingly important for engineers to rely on signal-integrity modeling tools, such as those provided by Ansoft, to simulate, characterize, and validate the performance of their packages.
To illustrate how these tools are used in a way that integrates smoothly into an existing design flow, consider the following scenario.
An ASIC company has specifically asked its packaging engineer to use an off-the-shelf BGA package for its layout that will meet the end customer's performance specifications and pass the measurement validation on the first pass. SPICE subcircuits also must be generated so that the ASIC company's design engineers can perform system-level simulations with their specified rise times of 100 ps.
The ASIC company's end customer also expects parasitic characterization for every net on the package, and the corresponding SPICE subcircuits for the traces to be generated and supplied.
For the fast edge-rate signals required for this package, an accurate signal-integrity modeling simulation is required. The package engineer uses Ansoft's Turbo Package Analyzer (TPA) to simulate the electromagnetic effects of this design and to generate a SPICE subcircuit.
To begin, a layout file, generated using an industry-standard layout tool from Cadence, Zuken or Synopsis, is imported directly into TPA (Figure 2). The only manual steps that are required are a verification of the layer stack-up and descriptions of the bond wire and via profiles. With the full three-dimensional details of the package successfully captured, the electrical simulation can begin. The partitioning algorithm steps through the entire package and creates 3D models for each net on the package, including coupling effects for adjacent structures within a predefined distance. Once the entire package is simulated and characterized, a full 3D broadband SPICE model is exported.
Figure 2: Full package view of a BGA Layout.
In this case, the SPICE subcircuit is a distributed Partial Element Equivalent Circuit (PEEC) that the ASIC customer's system-level engineers can use for system analysis in HSpice or PSpice (Figure 3). Since the design specifications that optimize the performance of this package have been determined, the PEEC subcircuit will allow the system-level engineer to accurately view and analyze signals throughout the entire device (Figure 4).
Figure 3: Spice Subcircuit.
Figure 4: Timing Plots.
After reviewing the resulting signal-integrity data, the package engineer and the system-level designer discuss changes and make modifications to the "off-the-shelf" package to achieve the electrical performance needed for their application.
After the design changes are implemented in their layout tool, the package is then recharacterized using TPA to verify its performance before committing to the time and expense of fabricating and validating the performance of the new design. After a successful system-level verification, the engineer can proceed with confidence in the production of the ASIC/package design.
This brief description illustrates the vital role that modeling tools play in the design process. These tools become even more crucial when signal rise times are faster than 500 ps.
Other analysis tools are used to address different aspects of high-speed design challenges. Radiation of signals with fast transitions and resonances in the power and ground plane of PCBs are among the phenomena that can be simulated using products such as Ansoft's HFSS' and SIwave'. The full-wave design solutions generated by these products provided power insight into the behavior of devices and also can be applied to generate highly accurate broadband SPICE models for system-level verification.
Today's high-speed designs have rise times that generate extremely wideband signals, making signal-integrity modeling tools an absolute requirement. As rise times continue to shorten and systems consume more bandwidth, the requirement for signal-integrity modeling increases. Therefore, having the proper tools will make the difference between a design pass or failure; between meeting development cost goals or going over budget; and between hitting the market window or missing it. Gordon Kelley of IBM Microelectronics and chair member of the JEDEC Solid State Technology Association, who spoke at a recent High-Speed Forum, agrees. "As frequencies reach farther into the GHz range," said Kelley, "full-wave analysis will be absolutely necessary."
Fortunately for package designers, today's signal-integrity modeling techniques can account for the ever-present 3D electromagnetic effects and, therefore, make it possible to reliably predict system-level performance. Moreover, this can be accomplished using the existing package design and analysis flow and is applicable to designs today and in the future.