Backplane architectures have been migrating from multi-drop buses to high-speed point-to-point serial communication links over the past few years. This has been driven by the need to develop more efficient non-blocking switching schemes between ingress and egress ports. An increase in capacity per port and port density per card has resulted in the need for backplane architectures that have capacity requirements where 640 Gigabit per second and greater are the norm. This is further compounded by architectures where the bandwidth capacity is increased in an attempt to ensure Quality of Service (QoS).
To address the need to transport a large amount of data from Point A to Point B, groups of high-speed serial links are ganged together with each link (or lane) sharing a portion of the overall data that needs to be sent between each point. So the rate required by each lane (not including any coding overhead) can be simplified to the total throughput required divided by the number of lanes. The larger the number of lanes, however, the greater the difficulty and cost in addressing ever increasing backplane capacity requirements. This is especially true for cards that provide any sort of switching (centralized or distributed switching elements). Thus, there is a desire to increase the data rate per lane in order to minimize the overall number of lanes required for data transmission. This focus on increasing the data rate has resulted in high-speed serial link technology being a driver in all-emerging electrical specifications, such as XAUI in 10G Ethernet or the High Speed Backplane Initiative.
The System Interconnect
High speed serial links consist of a transmitter, a receiver, and the copper medium, or channel, between them, as shown in Figure 1. In the past component vendors focused on the performance of their component in an isolated non-system like environment. As the high-speed serial links approach multi-gigabit data rates, Tyco Electronics has found that this approach to be insufficient, and has focused on understanding the entire system interconnect and the synergistic roles between the transmitter, receiver, and channel.
Figure 1. The System Interconnect
The Evolution of the System Interconnect
Designers face the task of developing architectures where every system interconnect must be able to pass data at the given rate of operation for all distances within the given architecture in a reliable manner. In a typical design activity, the various components of the channel were selected, based on their own individual performance capabilities, rather than on their performance in a system. The dielectric constants and loss tangents of the transmission media would be reviewed. Connectors were selected based on their impedance, cross-talk, and density characteristics. Finally, the devices were chosen for their ability to provide enough signal power to drive a given channel, while also having input and output impedances that matched the impedance of the channel to minimize reflections. This approach led to a limited understanding of the system interconnect and the underlying synergistic performance that was occurring, which was further masked by the relatively slow speed at which the system interconnect was actually running.
System interconnects that use devices that do not compensate for the behavior of the channel between them can be considered to be passive. These systems typically run at 2.5 Gb/s and lower, where losses in the system are normally predictable, and can be addressed through the selection of transmission media with better performance characteristics. Development efforts underway in the semiconductor industry, however, are causing the system interconnect to evolve from a passive to a sophisticated active nature. Figure 2 illustrates this evolution. Devices are now being designed to compensate for the predictable losses of the channel between the transmitter and receiver. This is allowing the design of systems that can run faster and over greater lengths than traditionally thought, and has reduced the need for system designers to use transmission media with better performance characteristics.
The need for increased bandwidth, however, has driven the frequency of operation upward, and into a region of performance where the synergistic influence between the various components of the channel can no longer be ignored. This interaction results in a channel with unpredictable losses. It is this unpredictable nature that limits the effectiveness of using better performing materials or devices intended to compensate for the predictable losses between the driver and receiver. Thus, it is the underlying passive channel that ultimately limits the speed of operation and length for which it may run.
There are two characteristics to the passive channel that will determine its data rate capacity- its ability to pass the signal and its inherent noise performance. To understand the synergy between the connector, the passive channel, and the active interconnect, Tyco Electronics has employed systems based on its Z-PACK HM-Zd connector, which is one of the lowest noise connectors available in the industry. (One of these systems, the XAUI HM-Zd Interoperability Platform has been selected by the 10 Gigabit Ethernet Consortium as a platform for its interoperability testing of XAUI devices.)
With the noise characteristic of channel performance minimized through the use of the Z-PACK HM-Zd connector, the signal throughput of the channel must be considered. Losses associated with dielectric loss of PWB material and trace skin effects are well known and documented, but can be considered predictable in nature, and hence correctable either with better material selection, wider traces, or through semiconductor techniques.
Unpredictable losses, however, can not be so easily compensated for. These losses are associated with the impedance discontinuities of the vias in the daughtercard and backplane that the connector is inserted into. Furthermore, the specific layers that the signal connects to on these boards will determine the nature of the unpredictable losses. Error! Reference source not found. illustrates the impact of the layer connection on the performance of the channel in the frequency domain. With a top layer connection, there is a significant roll-off in throughput in comparison to the bottom layer. The roll-off will translate to a reduced eye-opening and increased jitter. Therefore, one can expect the variation in performance to change as the thickness of the connector / board interface grows.
Figure 2. Evolution of the System Interconnect
Figure 3. Impact of Layer Connection on Signal Throughput
Figure 4 demonstrates how Marvell Semiconductor can compensate for the performance of the underlying passive channel by employing transmit de-emphasis at 3.125 gigabits per second. Essentially, the transmitter output is adjusted so that its lower frequency components are reduced in order to compensate for the channel's reduction of high-frequency components. This results in a better-balanced mix of low- and high-frequency content in the signal that reaches the output of the channel, resulting in lower jitter and ISI. Voltage constraints within semiconductor devices will eventually limit the effectiveness of de-emphasis at higher data rates.
Figure 4. The Effect of Transmit De-Emphasis
For serial data transmission at 10 gigabit per second speeds, equalization at the receiver has been shown to be an effective solution. Working with Gennum Corporation, Tyco Electronics demonstrated the synergistic performance of their device with the Z-PACK HM-Zd connector. Figure 5 shows an eye diagram at 10.7 Gbps. Using a channel based on bottom layer signal connections, the signal traversed the backplane through 2 HM-Zd connectors for a total length of 22" using standard FR-4. The eye diagrams are shown both without and with an equalizer. The Gennum GN2001 was easily able to recover the eye. Testing showed a BER of better than 10^-15 when tested over a period of two days (no errors found in 1.8x10^15 bits).
Figure 5. Eye diagrams over backplane trace. Total of 22 inches of trace, 2 connectors and 2 vias, at 10.7 Gbps both without (left) and with (right) equalizer
Designing for the Active Interconnect
Tyco Electronics has recognized that it offers a component for the Active Interconnect. Its relationships with semiconductor companies through its involvement in XAUI, HSBI, XFP, and 10 gigabit serial efforts has given it insight into the performance requirements for connectors in the Active Interconnect. This knowledge has been employed in other backplane product offerings, such as its MultiGig family.
The Active Interconnect concept is not limited to backplane applications either. Mezzanine and cabling may be used in topologies employing these chip techniques, so Tyco Electronics has used its knowledge in the design of its XAUI product family, which includes the Z-DOK mezzanine connector and the ZFP cabling solution. Furthermore, the PT family of products, which are used in XENPAK, XPAK, X2, and XFP, have also benefited from this knowledge.
John D'Ambrosia is the Manager of Semiconductor Relations for Tyco Electronics. John was an active participant in the development of 10 Gigabit Ethernet, and led the industry effort to develop interoperability testing between different suppliers of XAUI chips. Currently, he is serving as Secretary for the High Speed Backplane Initiative. He holds a BE EET from Pennsylvania State University and a Master's Degree in Engineering Management from NTU. John may be reached at email@example.com.