Over time, sample rates in Analog to Digital Converters (ADC) have increased steadily, due to some of the same technology improvements that have increased the speed and density of digital integrated circuits. Decreasing CMOS channel lengths and bipolar transistor base widths have resulted in devices that can operate at 100's of MHz and that provide sufficient gain for analog processing.
As silicon geometries shrink, they require lower power supplies, allowing for lower power dissipation while maintaining adequate breakdown voltage margin. IC power supplies have migrated from 5 V for TTL, which was the workhorse in the 1970's, to 3 V to 1.8 V and lower for CMOS; logic swings have been reducing commensurately.
Inclusion of digital functional blocks on the same silicon as analog blocks in mixed signal systems has resulted in high frequency analog processing in noisy environments, requiring specialized architectures and techniques at the chip level. This is also true at the printed circuit board level, where sensitive analog signals need to coexist with 'noisy' digital signals.
High-speed ADCs typically obtain some isolation from digital switching noise by maintaining separate power supplies on chip-one for the analog, and a second for the digital outputs. Stand-alone ADCs typically interface to variable and larger capacitive loads than integrated ADC cores. ADC cores typically drive a fixed internal load, with lower capacitance than that of the stand-alone device. Stand-alone ADC's also have more complex power bussing constraints. Lead frame and wire bond inductance effects become more important as edge rates speed up to meet high frequency operation demands. ADC cores can currently digitize at encode rates of 200 MHz or more at 12-bit resolution; in 1992 20MHz, 12-bit ADCs were considered state of the art.
Providing data outputs at these frequencies is a challenge. One solution is to multiplex the output data stream on to two separate output ports. This option reduces the output data rate by a factor of two, i.e. two 100 MHz buses provide an effective 200 MHz throughput. Obvious disadvantages are the increase in output pins required, and the synchronization issues encountered in multiple ADC systems.
Figure 1. Simplified LVDS Output.
A better solution, which can offer very high speed operation while minimizing complexity and maximizing performance, is the use of Low Voltage Differential Signaling (LVDS). LVDS is a new differential logic family that requires two pins for each signal, and is very well suited for high-speed digital transmission. It provides current outputs , and requires a 100-ohm termination resistor at the receiver input (far end of the line). The nominal output current per driver is 3.5 mA, resulting in a 350-mV voltage swing at the receiver's input.
Figure 1 shows operation with output signal V2 going positive by 350 mV and V1 going negative by 350 mV. This is accomplished by steering the 3.5 mA current provided by the constant current source from VDD through Q2, out to the external 100-ohm termination resistor, and back to the LVDS driver through Q3 to the on-chip current sink to ground. Pre-drive signals A+ and A-- establish the polarity of the output signals. Note that the LVDS output common mode voltage specification is approximately 1.2 V, and is maintained by a common mode control circuit that is not shown. The 100-ohm differential termination resistor translates the current output to a voltage and provides transmission line impedance matching to the two 50-ohm signal traces, minimizing transmission line effects such as reflections and ringing.
LVDS has some additional advantages over CMOS for ADC data output transmission. Standard CMOS logic runs out of gas at 125 MHz or so. Higher speed data transmission applications must turn to ECL, PECL and now LVDS. The differential outputs have an inherent common mode rejection advantage and can handle ground offsets between driver and receiver.
CMOS output buffers typically drive a load capacitance on the order of picofarads. The current required to charge and discharge this load in a nanosecond or so creates a voltage spike equal to L di/dt across the inductive power supply and ground pins on the ADC (ground bounce). This current surge is a source for electromagnetic coupling to the analog section of the ADC at the package level; this coupling results in ac performance degradation at higher analog input frequencies and/or sample rates.
LVDS, on the other hand, essentially steers a constant current through a termination resistor, so there is minimal transient load activity on the output supplies. This greatly reduces the potential for cross coupling of the outputs to the sensitive analog front end.
Datasheets for high-speed ADCs with CMOS outputs typically recommend that the ADC be placed close to the receiving logic to minimize the load capacitance and to avoid the deleterious effects of transient load currents. Unfortunately, this can place the ADC right next to a source of significant switching currents, radiation and heat generated by the receiving logic, ASIC, or FPGA.
An ADC with LVDS outputs provides balanced current outputs. The ADC can therefore be placed several inches or more from receiving logic, thus obtaining some physical isolation from noisy circuits. Figure 2 shows an FFT of the AD9430, a new 12-bit high speed ADC from Analog Devices. The AD9430 has data outputs that can be configured as LVDS or demultiplexed CMOS outputs. The FFT shows the ADC in LVDS output mode, with a sample clock of 210 MSPS, digitizing a 70 MHz analog input. For this test setup, an adapter board was built up placing 12 inches of PCB trace between the ADC data outputs and the receiving logic. An SNR of 63.7 dB was obtained. This was comparable to the performance obtained with the adapter removed, where the ADC was only driving an inch of PCB trace. In CMOS output mode the noise floor rose, degrading the SNR by 6 dB, when the 12-inch adapter board was placed at the ADC output.
LVDS signals tend to generate less EMI than single ended CMOS signals due to the differential outputs. (EMI generated by one output tends to be cancelled by the complementary output) Trace length skew between differential outputs should therefore be kept to a minimum to maximize this benefit.
Figure 2. FFT of AD9430 (LVDS Mode).
LVDS does have a disadvantage in power dissipation as compared to CMOS. LVDS power dissipation is constant and does not scale linearly with clock rates as in CMOS; at low sample rates CMOS can dissipate less power than LVDS. As sample rates increase, CMOS power dissipation will increase linearly with sample rate, eventually requiring more power than LVDS. At sample rates equal to 200 MSPS, LVDS and CMOS power dissipation are comparable.
LVDS does allow for very fast data transmission and edge rates, requiring that transmission line effects be considered in some applications. Some guidelines to follow in PCB design for LVDS:
- Place 100-ohm termination resistor close as possible to receiver
- Minimize trace length skew
- Avoid the use of vias if possible
- Maintain differential trace spacing along entire trace length
- Minimize 90 degree bends -- use 45 degree turns if possible
In summary, LVDS can provide for superior high frequency ADC performance while its inherent common mode rejection and reduced EMI can significantly ease high speed system design.