Despite the astonishing proliferation of wireless connections, analog POTS or "plain old telephone service" still delivers on price and availability. Credit card terminals and home security systems provide two of the older, more pass examples connected devices. However, growth in connectivity fuels new ideas and fosters novel expecta-tions. Let's listen in on a dialog between a well-connected vending machine and its supplier.
(Host modem) "Hello?"
(Vending machine) "Machine 127 here... today's sales were great, but I'm starting to run low. The temperature reached over 90F by noon for the last three days, so I increased prices by $0.25. Should I raise it another $0.15 until my supplies are replenished?"
Embedded modems are very different from the stand-alone modems found in PCs. Typical embedded modems have no attached "terminal" and the user interface (if any) is greatly simplified. The modem need offer only a few simple commands and options -- far fewer than implemented by the common "Hayes Command" set. In addition, an embedded system and its host tightly script the exchange of information.
Since the content exchange is relatively brief, high data rates are not necessary. Transmitting a kilobyte of information (which is significant for many embedded de-signs) at 300 baud usually takes less time than negotiating a high-speed modem connection. Cost and reliability remain the dominant considerations and 300 baud provides robust performance under conditions that give high-speed modems fits.
Lower data rates provide cost saving opportunities in the design of both the modem and the telephone line interface, known as the Data Access Arrangement (DAA). Low-speed modem chip sets often rely on an inexpensive, but dedicated microcontroller (MCU). Programmable System on Chip (PSoC) microcontrollers provide an unprece-dented path to further cost reduction -- thanks to its ability to dynamically reconfig-ure its peripheral capabilities.
Dynamic reconfiguration means that designers can tailor a single device to a particu-lar application, and then change functions on the fly -- re-using the same peripheral resources for a completely different task. For example, a PSoC device at the heart of an embedded application can easily morph into a modem, transmitting and receiving data. When the data transmission is complete, it can return those same peripheral assets to their primary functions in less than a millisecond. For many applications this means the modem is, essentially, free.
Back to Basics with the PSoC MCU
To fully understand how this works, it is necessary to start with a brief overview of the PSoC architecture. The PSoC MCU includes configurable analog and digital hardware blocks (known as PSoC blocks). Unlike a block of programmable logic, digi-tal PSoC blocks implement a predefined set of 8-bit functions. For wider functions, two or more blocks may be chained together. For example, two 8-bit PSoC blocks may be combined to create a 16-bit counter. Analog PSoC blocks contain op-amps with resistive feedback or switched capacitor arrays.
PSoC Designer, the integrated development environment (IDE) for PSoC microcontrol-lers, includes a complete library of "user modules" or predefined peripherals. User modules are represented graphically in PSoC Designer's Device Editor where they can be selected and assigned to specific PSoC blocks. Examples of digital user modules include timers, counters, pulse width modulators (PWM), dead band generators, pseudo-random sequence generators (PRS) and cyclical redundancy checkers (CRC). User modules for communication include Universal Asynchronous Receiver Transmit-ter (UART), and Serial Peripheral Interface (SPI') functions. PSoC designer automati-cally generates firmware to configure the PSoC blocks and provides Application Pro-gramming Interfaces (API) to speed development.
Building a 5-Cent Modem
This article outlines an implementation of a Bell 103 and V.21 compatible 300-baud modem using a PSoC microcontroller. The entire modem, shown in Figure 1, utilizes the Cypress MicroSystems CY8C26443 microcontroller, in addition to a minimal number of external capacitors and resistors. The PSoC MCU costs no more than tra-ditional, fixed-peripheral microcontrollers, so the incremental cost of adding a mo-dem to an embedded design can hover in the vicinity of 5 cents (excluding the DAA).
Figure 1. Assembled Modem Prototype
This PCB was designed for an enclosure with a simple keyboard to facilitate dialing and interaction with a remote PC. Components required to implement the modem and dialer are outlined in red.
The external RS-232 interface for this is shown in Schematic 1. The microprocessor interface sche-matic for this is shown in Schematic 2, while the DAA is illustrated in Schematic 3. The entire system is powered by a simple linear regulator (LDO) circuit (not shown).
The DAA isolates and protects the telephone system and the modem hardware from each other. Commonly, a transformer couples analog signals voice band signals be-tween the modem and telephone system. Optically isolated logic signals provide sim-ple status and control. Typically, the DAA asserts RING to signify an incoming call (not to be confused with the analog "Ring" signal paired with "Tip" to form the Telco line). To answer a call or pick up the line in order to dial out, the modem asserts an OFFHOOK signal. FCC Part 68 regulates Data Access Arrangement requirements in the US.
Bel-103 and V.21 standards specify full duplex communication using frequency-shift keying (FSK). The modem that originates the connection transmits data on a lower pair of frequencies and receives data from the answering modem on a higher pair. Table 1 gives the frequencies mandated by the two standards. "Mark" and "Space" designate the upper and lower frequencies in each pair, respectively. In the absence of data, modems send the Mark frequency. A byte to be transmitted is framed with a leading start bit and a trailing stop bit. Following the Start bit, data transmission proceeds least significant bit first. The Mark frequency represents a "1" bit and Space represents "0." Transitions between the two frequencies should be phase continuous to minimize noise. Intuitively, this means that when the frequency changes, the waveform should change in the smoothest possible fashion.
Table 1. Tone Pairs (in Hz) for Transmitting Data
Data arrives asynchronously by definition, but once transmission of a byte begins, bits should arrive at the nominal baud rate. Assigning the Space frequency to Start bits and the Mark frequency to Stop bits ensures that each byte begins with a Mark-to-Space transition, even when data is transmitted continuously. All data-related tim-ing is provided locally and referenced to this transition. The FSK modulator simply converts an outgoing serial bit stream into the time sequence of corresponding fre-quencies and the demodulator performs the inverse task.
Conversion between byte-parallel data and a serial stream with start and stop bits falls to a Universal Asynchronous Receiver/Transmitter (UART). UART receivers as-sess the value of an incoming bit by testing its value at or around the middle of the bit time. For correct interpretation of a stop bit tested at 95% of the way through a 10-bit sequence (halfway through the 10th bit), the sum of all timing errors across the connection must not exceed 5%. Sources of error include timing inaccuracy in the transmitter, in the receiver and as well as errors induced by line impairments. Inter-symbol interference, the overlapping of the Mark and Space frequencies, also con-tribute to the error.
PSoC Modem Overview
The PSoC Modem project implements three major functions: a transmitter, a receiver, and the optional DTMF (dual tone multi-frequency) generator for dialing. The trans-mitter contains a hardware modulator and software for Start/Stop framing and parallel-to-serial conversion. The Receiver contains the demodulator. It can be config-ured for an off-chip UART or, alternatively, for an internal UART implemented in software or by a digital PSoC communications block. Figure 1 illustrates the partition of each of these functions into hardware and software components.
Figure 2. Overview of the PSoC 300 Baud Modem
"Modem" derives from the contraction of the words "modulator" and "demodulator," functions implemented in the transmitter and receiver sections. The DTMF dialer uses the same hardware peripheral blocks subsequently reconfigured to implement the transmitter. Shading identi-fies features implemented in software.
The PSoC Modem project organizes and specifies all DTMF Dialer hardware resources and related options within a distinct configuration labeled "Dialer." This configuration (or hardware overlay) can be dynamically loaded just prior to dialing a telephone number. The PSoC blocks employed by the dialer are later reutilized by the transmit-ter, but in a completely different way. The configuration named "Transmitter" keeps its requirements, settings and options separate from those of the Dialer. The PSoC Designer IDE automatically generates source code to swap between these configura-tions. Figure 3 shows the transmitter configuration window cascaded on top of a window displaying the DTMF Dialer overlay.
Figure 3. Dynamic Reconfiguration in the Device Editor
These partial Device Editor views show the Dialer and the Transmit-ter configurations. A configuration can customize just a few PSoC blocks, pins, busses and/or global parameters, or even the entire device.
PSoC Designer incorporates a DTMF generation user module. Instantiation of this pe-ripheral within the Dialer overlay greatly simplifies implementation of the Dialer's functionality. The instance, mapped onto PSoC blocks DCA07 and ASB13, appears in Figure 3. This user module provides a waveform generator integrating a 6-bit DAC and an 8-bit timer to generate interrupts at the output sample rate. Setting the user module parameters for a 32 kHz update rate and adding an external RC filter limit harmonic distortion to less than 2% and provide sufficient rejection of the image to meet the out-of-band noise requirements of FCC part 68.
This user module employs a sine-wave lookup table and the techniques of a numeri-cally controlled oscillator. The time period set by the interrupt rate corresponds to a specific phase angle for each of the two frequencies to be generated and summed. Each phase angle corresponds to a forward displacement in the table (modulo the ta-ble size) from one "sample" to the next. The sample for the lower frequency of the pair is scaled by -2dB and added to the sample for the higher frequency to obtain the out-put value for the DAC.
Two additional user modules complete the Dialer configuration. The instance name "GainBuf" was assigned to the first of these user modules and it was mapped onto PSoC block ASA23. In this case, a multiplying DAC based on switched capacitor technology was selected rather than a programmable gain amplifier with resistive feedback. Either would suffice, but selecting the discrete-time multiplying DAC sim-plifies the connection from the DTMF DAC. The multiplying DAC provides 6-bit reso-lution of the multiplicand and 2 different output ranges. This offers finer control than the PGA. The PGA, on the other hand offers gains of up to 16 over 8 times greater than the multiplying DAC's maximum gain of 31/16.
Convenience, rather than necessity, suggests selection of the final user module in this configuration -- "DialerClk." This user module instantiates an 8-bit timer to serve the two PSoC blocks assigned to the Dialer user module. Reasons beyond the scope of this article dictate the time base for the Dialer user module's DAC to be at least 4 times faster than the update rate and, in any case, no slower than 4 times 32 kHz . Upper bounds on the time base preclude direct use of the fixed 24 and 48 MHz sys-tem clocks. However, dividing the 24 MHz system clock by 75 with an 8-bit timer produces a 320 kHz output that is suitable for update rates of 32 kHz .
A DAC-based implementation of an FSK modulator offers several attractive advan-tages including reuse of DTMF generator code and the maintenance of its inherent phase continuity. An alternative strategy proved more desirable, however, because it entails very little code space and requires minimal CPU overhead while using the same number of PSoC blocks.
This alternative approach utilizes a digital block to generate a square wave with a 50 percent duty cycle at the mark or space frequency, and smooth it with a switched ca-pacitor filter and an external RC pole. This is easily achieved using a pulse-width modulator (PWM) user module, which requires an input clock and two parameters -- period and duty cycle. Period is the divisor of the source clock that sets the output frequency for a given input clock. Setting the duty cycle parameter to half the value of the period yields the intended result of 50-50.
Excellent phase continuity is the happy-if not immediately obvious-result of hold-ing the period fixed and modulating the source clock to produce the desired output frequency. To understand this intuitively, imagine that the source clock divides time into little packets. If you increase its frequency, the packets get a bit smaller. The PWM stuffs these packets into two chutes labeled "logic-high" and "logic-low." If the PWM period is N and the duty cycle is 50%, it puts N/2 packets in one chute, then N/2 in the other, mindlessly alternating back and forth between the two every N/2 packets. As long as all packets are all the same size, a 50% duty cycle results.
However, if the packets abruptly get a little smaller (or larger) the amount of time be-ing stuffed down the current chute also grows smaller (or larger) by an amount corre-sponding to the number of "new" packets that make up that chute's allotment. Thereafter, the duty cycle returns to 50% as the packets going into each chute stay at the same new size. The boundary between two packets of different size marks not only the point at which the PWM frequency instantaneously changes, but also a phase of each frequency. If the boundary occurs between packet M and M+1 the phase of each one must be 2pM/N. Clearly, for the smallest workable value, N=2, the phase changes continuously, always on a multiple-of-p boundary. You can now see that N determines only the granularity of phase boundary and that the result is al-ways phase continuous.
A transition from one frequency to another signifies a change between the value of two adjacent data bits or the beginning of the all-important start bit. Consequently, the granularity determined by N (or, equivalently, the size of the packets) sets a lower bound on the modulation bit-time jitter. Larger values of N (smaller packets) mini-mize this contribution to system timing error. The modulator uses the 8-bit timer user module "XmtFreq" to control the size of the packets. The PWM user module, "XmtScale" has a period, or N, of 118. Thus, the worst case bit-time jitter of 1/118th of a cycle or about 8 msec at 1070.4 Hz represents a contribution of 0.2% to the sys-tem timing error.
An interrupt service routine (ISR), driven by an 8-bit timer ("HostComm"), controls start/stop bit generation and data serialization. Because this ISR provides other im-portant services, it could be assigned to either the transmitter or receiver overlay. Both are loaded during modem operations, since they must execute in parallel. Host-Comm interrupts occur at 2400 Hz, so only one of every eight interrupts must decide whether to transmit another bit. Every 300th of a second, HostComm's ISR performs a 1-bit shift of the data byte, forcing the next bit into the Carry bit of the CPU's Flag register. The value appropriate for generating the Mark or Space frequency is placed in the XmtFreq period register as determined by the carry flag.
POTS circuits may attenuate the signal by 40dB or more by the time it spans the network. Therefore, separating the received from the transmitted signal is of first im-portance. The Receiver configuration uses a differential amplifier to subtract the transmit signal from the composite transmit/receive waveform. While 60dB of rejec-tion is possible, it is sensitive to line impedance and 10db of rejection is a more real-istic figure. Following the differential circuit, a four-pole band pass filter provides an additional 20 to 25dB of rejection. Beyond this, the detection algorithm demonstrates good tolerance to moderate levels of crosstalk from the transmit channel. Next, an 8-bit Delta-Sigma ADC digitizes the input at 7500 samples per second. This provides 25 samples per bit time.
The foundation of the Differential Detection algorithm rests on the trigonometric identity,
Generally, mixing two sine waves produces two new sine waves, one at the sum of the two original frequencies and another a frequency equal to the difference between them. Next, suppose that one is merely a time-delayed version of the other:
The equation becomes
The "sum term" is double the original frequency and the "difference term" reduces to a DC offset that depends on the phase shift induced by the time delay. For a given frequency, different time shifts produce different offsets. Conversely, for a fixed time delay, different frequencies will produce different offsets. Restated, if we correlate the received signal with a time-delayed version of itself, then the DC offset produced at the Mark frequency will differ from that at the Space frequency. Using a digital filter to eliminate the 2a frequency component leaves just an offset that distinguishes be-tween Mark and Space.
For optimum discrimination, we need to choose a delay that maximizes the difference between the offsets,
The calculation is a simple. For the Bell 103 answer-mode pair, 2025 and 2225 Hz, a 22 sample delay appears optimal, but 15 samples comes very close. Modeling the al-gorithm with Matlab provided an opportunity to test the effects of frequency error, transmit rejection and signal-to-noise ratio (SNR) on the performance of the algo-rithm. Figure 4 shows graphical output from the model.
Figure 4. Model of Detection Algorithm for a Sequence of 100 Bits
The top graph shows noise and crosstalk from the transmitted signal which have been added to the receive signal (in magenta). The middle graph shows the results of filtering the differential detector's output with a "perfectly" clean input and with the noisy signal from the previous graph. A 30-tap FIR was applied to the clean output; an 8-tap FIR to the noisy output. The bottom graph reproduces the clean waveform and su-perimposes the result of applying a zero-crossing detector to the output of the 8-tap FIR.
The modem performs well in a variety of circumstances. Bit error rates (BER) better than 10^-7 have been measured under ideal circumstances. Figure 5 depicts live op-eration of the demodulator under somewhat trying circumstances. Future plans in-clude formal evaluation of performance under standard test conditions.
Figure 5. Reception of the 8-bit ASCII Character "a"
The lower trace displays the input to the 8-bit Delta Sigma ADC; the upper trace a direct logic output of the differential detection algorithm. The analog input exhibits evidence of significant transmit signal crosstalk resulting from to an induced impedance mismatch between the modem and the phone line.
The PSoC Multiply/MAC unit facilitates implementation of the autocorrelation and the digital filter routines by reducing the amount of code and the CPU cycles. At 24 MHz, the CPU overhead required to support operation of the modem falls under 20% while continuously streaming full duplex data. The differential detection algorithm accounts for most of it. Approximately 3kB of Flash and 64 byes of RAM are required for a basic modem implementation. Depending on the options selected, 5 to 6 digital PSoC blocks and 9 analog PSoC blocks are consumed during modem operations. The pin count ranges from 9 to 11 depending on the choice of UART receiver. All PSoC blocks can be dynamically reconfigured for arbitrary purposes after modem operation ceases.
A functional, robust 300-baud modem based on the PSoC microcontroller is feasible in many embedded designs. Furthermore, it can be accomplished inexpensively with-out adding hardware other than the DAA required by every modem - no data pump, no controller chip and no active filters. This clearly shows that dynamic reconfigura-tion of peripheral assets can simultaneously increase functionality and reduce part costs. PSoC provides the ability to change designs radically, in midstream, without changing or adding parts- both during the development process and later, right in the field.
Design with a PSoC device places the emphasis on "Programmable System", not just programmability. The overall complexity of the project described here differs little from what we would encounter using a traditional microcontroller and other neces-sary components. The PSoC Designer IDE helps reduce system-level complexity through a consistent graphical user interface, tight integration between its hardware and software development environments, a design flow that facilitates easy movement between them and built-in user module documentation.
1 Clare Inc., CYG20XX Cybergate, Datasheet DS-CYG20XX-R1, 2000.
2 Cypress MicroSystems, CY8C25122, CY8C26233, CY8C26443, CY8C26643 Device Data Sheet CMS100002A, 2002.
3 Cypress MicroSystems, PSoC' Designer: Integrated Development Environment User Guide, CMS10005A, 2002.
4 J. A. C. Bingham, The Theory and Practice of Modem Design, John Wiley and Sons, New York, NY, 1998.
Many individuals contributed to this work. The author is indebted to coworkers Den-nis Seguine, Jeff Dahlin and Dave Van Ess for help with the analog interface, modu-lator and DTMF generator. Dave Bordui of the Cypress Design Center first demon-strated that a Bell 103 modem was possible. Professor Jim Ritcey of the University of Washington proposed the differential detection algorithm and assisted in modeling the detector.