Advanced integrated circuits such as communication processors achieve increased performance, added functionality, and reduced power consumption by being fabricated using the latest sub-micron technologies. This results in reduced operating core voltages. Increasingly, inter-device communication standards also require the use of a variety of I/O supply voltages. These factors result in devices, cards and systems with multiple power supply requirements.
An asynchronous transport mode (ATM) port card serves as an application example. Figure 1 shows the devices used on a typical ATM port card-along with its back plane interface and power supplies. The table summarizes the power supply requirements for each multi-voltage devices. Some use a 1.5V core; some use 1.8 volts; some 2.5 volts. All have 3.3V I/O requirements.
Figure 1: An ATM port card with multivoltage devices.
Table 1: Individual device power supply requirements range from 1.5V cores to 3.3V I/O.
Although the power supply requirement of each device, taken separately, should be easy to implement, satisfying all requirements (along with sequencing requirements) on this ATM port card be quite complex.
Apart from the requirements of individual devices, the design also calls for monitoring power supply voltages during normal operation. If any supply voltage falls below threshold, the CPU should be reset and the power supply to all devices should be recycled.
Five discrete operations
Overall system power supply activity can be subdivided into 5 phases. Figure 2 shows the sequencing requirements in the corresponding boxes. The actual power supply functions during those phases are indicated below the box. (A power control circuit using Lattice's ispPAC Power Manager, the Power1208, is shown in Figure 3.)
Figure 2: The five power supply phases of the ATM port card. (The sequence of power supply functions during those phases is indicated below the box.)
Figure 3: Power management of the ATM port card can be accomplished with the ispPACPower1208. The device will wait for the 5V and 3.3V input rails to stabilize before turning on other devices.
The tracking requirement of the network processor (the PowerQUICC) can be implemented using the bootstrapping method. However, it results in a non-monotonic ramp of 3.3V at the CPU's I/O pins. While that non-monotonic nonmonotonic ramp is OK with the CPU, it does not conform to the backplane interface's (the ORT82G5) power supply requirement. Hence we need to route the 3.3V through another power supply MOSFET. The power supply sequence of the SONET ASIC is opposite to that of the sequence of the CPU and ORT82G5. To address all requirements simultaneously, we need five power supply busses in this card. The supply busses are listed as follows:
1. The 1.8V supply is generated using an 1.8V LDO (Low Drop Out regulator) for CPU's core.
2. The 3.3V for the CPU's I/O is fed through a power MOSFET (Q1 in Figure 3). To facilitate independent ramp rate control, the MOSFET that power the bus interface I/O (Q3 in the circuit) is driven by the same signal from the power manager.
3. The 1.5V for the core of ORT82G5 is generated using the permanently enabled 1.5V brick (dcto- dc converter). A MOSFET (Q4) is used to provide a monotonic ramp for the core supply.
4. The 3.3V for the ORT82G5 and SONET ASIC is supplied through a MOSFET (Q3) used as a series-pass element. This supply is enabled along with the 3.3V of the CPU
5. The 2.5V for the SONET ASIC is generated using a 2.5V brick, sourced from the 5V back plane source. The enable signal is controlled to meet the sequencing requirement of the ASIC.
The Power1208-a programmable mixed-signal device-is one of the few ICs capable of controlling all of these power supply management functions from a single chip. By combining Lattice's ispPAC programmable analog and ispMACH programmable logic technologies, the Power1208 becomes one of the first mixed signal PLDs. Specified for operation from 2.25V to 5.5V, the ispPAC Power Manager family provides a high level of functionality for implementing on-board power supply management solutions. The Power1208 implements power supply sequencing, monitoring, and supervisory functions for any printed circuit board using multiple voltage supplies.
On-chip features include a 32-input, 16-macrocell CPLD sequence controller, 4 delay timers (for sequence delays and watchdog timers), and a 250- kHz oscillator for timing and clocking the CPLD. There are 12 analog inputs (each with programmable precision analog threshold from 1.0V to 5.75V in 192 steps), and 8 comparator outputs. Also selectable are 4 programmable high-voltage N-channel MOSFETs (with programmable charge current ranging from 0.5mA -50mA and 8-to-12V). Finally, the part includes 4 general-purpose open-drain digital logic outputs and 4 logic inputs.
Figure 4: Oscilloscope waveform showing 1.8V and 3.3V tracking at the PowerQUICC network processor.
Some assembly required
Correlating these hardware resources of the ispPAC power manager with the power supply phases will require some analysis. During Phase 1,the ispPAC Power Manager device waits for 5V and 3.3V inputs to the card to stabilize using the signals "Good_Input_ 5V signal and Good_Input_ 3V3" respectively.
The Phase 2 is implemented as follows: The 1.8V LDO and 1.5V FET are turned on together; this will power the core of the CPU and through the Schottky diode (connected between the CPU's I/O and the and its core). The I/O voltage also closely follows the core voltage -meeting the tracking requirement. At the same time the power supply to the ORT82G5 core also monotonically ramps up.
Once the 1.8V and 1.5V sources stabilize, the 3.3V supply is turned on through both MOSFETs Q1 & Q3. Initially, the CPU's I/O pin stays at 1.8V through the schottky diode. When the 3.3V source raises above 1.8V, the schottky diode is automatically turned off and the I/O pins follow the 3.3V MOSFET Q1's output. Simultaneously, 3.3V is applied to both the ASIC and the ORT82G5 devices through the MOSFET Q3. After the 3.3V stabilizes at the ORT82G5 and the ASIC I/O supply, the 2.5V brick is turned on, thus meeting the supply sequence requirement of the SONET ASIC. (The exact waveform is shown in Figure 4.)
Phase 3: After ensuring that the 3.3V and 1.8V at the CPU are stable, a 60 ms timer is started. After that timer is expired, the "CPU_Reset" signal is de-asserted. This results in stretching of the reset pulse for the CPU.
Phase 4: The card signals to the main controller that the card is turned on correctly. This is done by asserting the "Port_Card_OK" signal. Subsequently, all power supply voltages are monitored continuously for faults. When faults occur (for example, one of the supplies falls below a defined Vccmin threshold), the "CPU_Reset" signal is asserted and the device logic transitions to phase 5.
Phase 5: Here the power supplies for the ASIC and ORT82G5 devices are turned off immediately. In order to meet the power supply turn off tracking requirement, the following steps are implemented in sequence. First, the 3.3V to the CPU is turned off while the shorting FET (Q2) is simultaneously turned on, thereby shorting the CPU's I/O pins to core voltage. The manager waits for a few milliseconds for the I/O decoupling capacitors to discharge, then turns-off the core voltage (1.8V) to the CPU.
As can be seen, the isp PAC Power Manager device controls the sequencing and monitoring of power supplies efficiently while generating required supervisory signals. Understanding the features and capabilities of the of the ispPAC power manager device greatly helps design implementation with the PACDesigner software.
Implementing power supply management on the ATM port card can be implemented using the PAC-Designer Software. Analog control designs that sequence and monitor power supplies can be implemented on Power1208 devices using Lattice's PAC-Designer tools, version 2.0. The PAC-Designer software is an intuitive PC-based schematic design entry and simulation tool. The user can design complex sequencing and monitoring functionality easily using PAC- Designer's newest feature, LogiBuilder, which uses a series of easy-to-use pull-down menus.
To implement the ATM design using the PACDesigner software, complete the following steps:
1. Set Monitoring threshold values for each analog input by selecting the appropriate threshold value from a pull down menu.
2. The Power Supply Ramp Rate Control is implemented by setting the MOSFET gate drive characteristics for the HVOUT outputs. This is set by a pull down menu as well.
3. Power Supply Sequencing, Tracking and Supervisory Signal Generation Logic can be defined easily using just five point-and-click instructions in the LogiBuilder section.
4. Verification using PAC-Designer's waveform simulator can verify the completed design.
5. ispDownload to Power1208 Device-The complete and verified design can be downloaded to the Power1208 device through the device's JTAG port.
Once the interface to the power supply busses and the MOSFET are specified, the actual power supply sequencing and monitoring steps are designed using the LogiBuilder. The LogiBuilder program steps that correspond with the 5 power supply phases of power management are:
- Phase 1-Step 0 and Step 1-Waiting for input power supplies to stabilize
- Phase 2-Step 2 to Step 8-Applying the correct power supply to each device
- Phase 3-Step 6 and Step 7-Pulse stretching of CPU-Reset
- Phase 4-Step 9 and Step 10-Card normal operation
- Phase 5-Step 11 to Step 13-Turning the power supply off
This LogiBuilder program is then compiled and the resulting JEDEC file is then downloaded into the ispPAC Power Manager device through its JTAG pins.