SAN FRANCISCO Semiconductor industry representatives from around the world gathered here Wednesday (July 16) to consider changes such as adding wireless communications technologies to the 2003 International Technology Roadmap for Semiconductors.
The draft presentation discussed here will be presented to the full ITRS committee for approval on Dec. 2 at a roadmap meeting planned for Taipei, Taiwan. It will then be published as the 2003 update to the ITRS.
Among the major alterations likely to be approved are adding technologies for wireless communications, including silicon germanium, gallium arsenide and indium phosphide. If approved, it would be the first time the roadmap has included non-silicon technologies, said Paolo Gargini, the chairman of the roadmap committee, and director of technology strategy at Intel Corp.
The wireless chapter will include four working groups: power management; RF and transceivers; analog and mixed signal; and frequencies of up to 100 GHz.
The meeting tentatively approved extending the chapter on emerging devices. The chapter at least in part responds to the formation of a nanotechnology lobby that tends to exclude silicon-based devices from the nanotechnology definition, even though chips have entered the nano realm.
More fundamentally, the extension is a recognition that the ITRS needs to get its arms around the post-CMOS era, when CMOS runs out of gas in the 2010 to 2015 time frame.
"This is the first element toward building a bridge" to the post-CMOS era. The semiconductor industry has to get involved now, or it won't be ready when "silicon runs out of steam," Gargini said.
Also, the conference here approved the study of immersion lithography as a possible addition to the roadmap, with the 45-nm node the target for deployment. The addition is "based on faith, on what little we know today. It is something we going to look at," said Gargini.
Extreme ultraviolet lithography remains the leading candidate at the 32-nm node and beyond, he added. While optical lithography now is believed to be workable at the 45-nm node, "it will be tougher to field optical lithography for the 32-nm node," he added.
The conference also said it will begin to discuss the merits of imprint lithography. It also proposed removal of the X-ray and projection ion beam forms of lithography from the lithography roadmap.
The conference also approved studying wafers with a 450-mm diameter, starting in 2005. Gargini said moving to a larger wafer size becomes important if the industry is unable to maintain Moore's Law, scaling transistors to half their size roughly every two years. In order to reduce costs, the shift to a larger wafer size has tended to make up for gradual slippages in the ability to move to a new process generation in two years.
Depending on whether or not the two-year cycle can be maintained, the 450-mm wafer dimension may be needed in 10 years. The push for 300-mm wafers began in 1994 with the formation of the I300 consortium. The drive for a 450-mm generation may take another decade, or longer, to work out the materials and equipment issues surrounding the shift to a larger wafer size, Gargini said.
Results from the meeting, held in conjunction with the Semicon West conference, will be posted in about a week to the Sematech Web site.