YORKTOWN HEIGHTS, N.Y. The next generation of semiconductors will be carbon-based if researchers at IBM's T.J. Watson Research Center here have their way. IBM revealed details Monday (May 20) about what it is calling "the world's best transistor," based on a single carbon nanotube measuring 1.4-nanometers in diameter. Fabricated with conventional MOSFET processing technology, IBM characterized both n-type and p-type FETs using carbon nanotubes as the channel.
"It will be several years before CNFETs carbon nanotube field-effect transistors are ready for commercialization, but these results indicate that they will outperform even the most advanced silicon transistor designs," said Phaedon Avouris, manager of nanoscale science at IBM Research.
Avouris previously described plans for top-gate CNFETs last October at the Nanotube Symposium in Tsukuba, Japan. Monday's announcement reveals details about its implementation of top-gate CNFET prototypes from a paper Avouris published in Applied Physics Letters (APL). He collaborated on that paper with researchers Shalom Wind, Joerg Appenzeller, Richard Martel and Vincent Derycke at IBM's T.J. Watson Research Center here.
Avouris said that IBM had eliminated its previous use of a bottom gate that forced all CNFETs on a chip to switch simultaneously. Its current CNFETs instead utilize a conventional top-gate electrode above the conduction channel so that each transistor can be switched independently. Avouris also revealed that its gate dielectric had been slimmed down from 150 nm on the older bottom-gate design, to 15 nm on the newer top-gate. The thickness of a circuit's gate dielectric is inversely proportional to its switching speed.
"Even in their un-optimized state, our current CNFETs outperform the most advanced silicon designs. After we have had time to optimize our CNFET designs, we could get another order of magnitude or more improvement," said Avouris.
In the APL paper, IBM revealed details about its characterization of top-gate CNFETs, such as their steep subthreshold slope and high transconductance. In tests conducted by IBM, its CNFET prototypes, even in their first-generation un-optimized state, bested the fastest, highly optimized, next-generation silicon designs on several metrics. For example, they two to four times as much current carrying capability, the company said.