HILLSBORO, Ore. Intel Corp. researchers will introduce a tri-gate transistor structure at the International Solid-State Devices and Materials conference in Nagoya, Japan on Tuesday (Sept. 17), the latest contender among a variety of post-planar CMOS devices.
Gerald Marcyk, director of components research at Intel's logic development center here, said the tri-gate transistor is a candidate structure that may be introduced as early as the 45-nanometer process node, which is expected to move into manufacturing in 2007. For the tri-gate, Intel turned to a box-like structure in which the width and height of the transistor channel are equal to the length of the transistor gate.
Intel has created tri-gate prototypes using 130-nm design rules and 65-nm gate lengths, and found that drive current improved by about 20 percent compared with planar structures. The leakage current improved by a factor of about 10 to 100, similar to the power improvement seen with the fully-depleted silicon-on-insulator (SOI) planar transistors.
"We at Intel, and others in the industry, believe that we are getting closer to a fundamental shift in how we make transistors, largely because of leakage and power considerations," Marcyk said. "We need a different kind of structure, and we believe this tri-gate structure is a good step. But I can't say it is the final step."
Intel has demonstrated conventional planar transistors on bulk silicon with gate lengths of 20 nm, and saw the kind of performance and density gains expected from brute scaling. But the Ioff leakage current was found to be much too high for microprocessors with 100- to 200-million transistors.
Leakage current is kept under better control in a fully-depleted planar SOI device, but Marcyk said the threshold voltage of such a device can vary widely unless the thickness of the silicon layer is precisely controlled. And a fully-depleted SOI planar transistor might require an active silicon layer as thin as 10 nm a difficult manufacturing target, he said.
The tri-gate structure is much less sensitive to the thickness of the silicon layer, compared to a planar structure, Marcyk said.
Meet the candidates
At this year's International Electron Devices Meeting (IEDM) scheduled for Dec. 8-11 in San Francisco, several companies will introduce FinFET devices, in which a raised fin-like structure controls double-gate devices. Taiwan Semiconductor Manufacturing Co. Ltd. will introduce a horseshoe-shaped structure, called the omega FET.
However, Marcyk said that the width of the fin in a FinFET is smaller than the gate length. Because the width is smaller, lithography would have to be extended, or advanced, to finer linewidths in order to pattern the fin. If the device were to have a 30-nm channel, for example, it could need a 20-nm wide fin.
To create a fully-depleted tri-gate transistor with a 30-nm gate length, the thickness of the silicon can be kept at 30 nm, a more manageable challenge than the 10-nm silicon thickness that could be required with a planar fully-depleted SOI-type device, he said.
"The triple-gate devices are very scalable to smaller sizes. But this is just a possibility, one candidate. We are also considering planar devices, and non-silicon approaches to the 45-nm node. We want to give our manufacturing people the best option to pick from. We do believe the geometry control of making these fins is viable, but clearly it will take years of work to make them manufacturable.