Xerox Corp.'s Palo Alto Research Center (PARC) has developed a technique for creating self-assembling 3-D structures on IC substrates. PARC has demonstrated the technique by creating out-of-plane inductors and dense interconnection systems, and is now looking for partners to commercialize the technology, trademarked StressedMetal.
The process uses established semiconductor techniques that PARC says could be adopted in most semiconductor fabrication facilities. It uses sputtering to deposit films with a built-in stress gradient so that when they are patterned and released from their substrate, they curl into a designed radius of curvature. These shapes can be designed to curl up enough to create dense interconnects or to curl over in pairs to form inductor coils.
The technique has been applied to a high-Q, out-of-plane inductor. It can be built on substrates including active circuit wafers, making it potentially useful for RF applications such as cellphone ICs. The coils are built using the StressedMetal technique, which uses four mask steps, and are electroplated with copper to form the coil windings.
PARC claims the coils have a Q factor of 70 at 1 GHz when built on a standard CMOS substrate. The coil also has very low losses because its out-of-plane design stops the magnetic flux penetrating the substrate, where it would create eddy currents that would dissipate the electromagnetic field's energy.
PARC says the coil's Q results are twice as good as any other inductor integrated on a semiconductor. The StressedMetal technique has also been used to build a high-density interconnection system for complex ICs and optoelectronic systems.
Stress-engineered springs were formed to create a comb of contacts with more than five times the density of current commercial packaging.
PARC demonstrated the spring interconnect as part of its effort to build a solid-state imager for laser printing. The imager has an array of vertical cavity surface-emitting lasers (VCSELs), with laser elements staggered 3-micron apart. A stress-engineered thin film was patterned onto the wires addressing each VCSEL and, on release, the film stress forced the ends to curl.
Packages were formed by pressing the springs against a set of device contact pads and protecting the joints with glue. The result was a set of 200-element laser arrays with pads 4-microns wide on a 6-micron pitch connected to silicon CMOS driver chips.