SALT LAKE CITY Sun Microsystems vice president Ivan Sutherland laid out an integrated path to asynchronous chip design at the Async 2001 conference held Mar. 11-14 , proposing that developers look to win the system-clock GHz race by eliminating the clock.
Sutherland has long been known for bold ideas. In the '80s, he pioneered the computer graphics industry; in 1990, Sun bought his consulting company to make it the nucleus of Sun Microsystems Laboratories. Sutherland's current brainchild at Sun Labs, FleetZero, is "still five years away from commercialization," he told his conference audience, but the prototype chip "shows how to eliminate system clocks and get much faster chips than are possible by just increasing system clock speeds."
The continuous rise in clock speeds fueled by an almost religious devotion to synchronous chip architectures among designers has repeatedly been predicted to be approaching the point of diminishing returns. Clock skews alone were theoretically supposed to render gigahertz speeds impossible. But synchronous-chip designers have continually found ways around such potential limits.
Nevertheless, conferences like Async 2001 are testimony that asynchronous chips that is, chips that do not slave all their internal operations to an external system clock are inevitable. But if Sun Microsystems' FleetZero architecture pans out as advertised, asynchronous chips may become desirable in and of themselves, outperforming synchronous chips with equivalent silicon real estate.
"Benchtop tests performed using the FleetZero chip demonstrate throughput of 1.2 billion data items per second which is faster than a synchronous device using the same 0.35-micron CMOS process and our simulations suggest that much faster chips are possible with more-modern process technologies," said Sutherland.
FleetZero replaces synchronous arithmetic operations with data-movement operations among asynchronous processor blocks called ships. In place of synchronous chips' instructions are binary codes that specify the routes data items need to take among the processor blocks to accomplish the same tasks that synchronous chips perform via sequential operations. Software compilers would manage on-chip communications, routing data among the asynchronous blocks.
Sun Labs claims its processing ships will scale up gracefully to "flotillas" of systems-on-chip. Making data communications not logical operations the core problem of computing will lower costs, quicken overall execution speeds and cut power consumption compared with synchronous designs, Sutherland contends.
"Communications on a chip has become the most important chip-design problem," he said. "Not only do the wires by which chips communicate their data occupy more space than the transistors, but they are also slower and consume more power. FleetZero puts the compiler writer in charge of the wires, making much better use of computing resources."
According to four papers presented by Sun Labs at Async 2001, today's chips underutilize their silicon resources by as much as 20 times, because the optimal transistor switching times must be slowed so that all resources remain in sync with the external system clock. Even other asynchronous models, such as "data flow," retain a von Neumann-like adherence to logical and arithmetic operations. And they fail to enforce the timing constraints needed to recover the twenty-fold underutilization of chip resources, Sutherland said.
In contrast, FleetZero provides data-routing resources engineered by Sun Labs to dovetail with current chip-making capabilities. The primary directive at Sun Labs was to enable processing-block transistors to run at optimal switching speeds while communicating their results among processor blocks using minimal chip real estate.
The resulting architecture uses concepts that divide chip real estate into two-dimensional parcels among which data flows using short wires instead of long bus lines. Wires are multiplexed across the silicon real estate using two-dimensional shapes called horns to broadcast data and shapes called funnels to concentrate data.
FleetZero simplifies the compiler writer's job by enforcing standardization among processor blocks. An approach called GasP allows no more than six gate delays. Instructions, which are essentially lists of "move" commands, can then be delivered to the enable-inputs of the internal latches by a minimal first-input/first-output, at a pace determined with an asynchronous three-inverter ring oscillator.
In an Async 2001 paper on GasP, Sutherland and Sun Labs researcher Scott Fairbanks described the circuit primitives used for FleetZero's self-regulating processor blocks, contending that GasP circuits reduce the number of transistors required to flow data among processor blocks by using self-timed data branch and merge commands to move chip data like a traffic cop.
In a third paper, Sutherland and Sun Labs researcher Jo Ebergen proposed a set of schematic symbols to represent the actions of GasP asynchronous circuits graphically.
And in a fourth paper, Sutherland, Lexau and Sun Labs colleagues William Coates, Ian Jones and Fairbanks described the prototype chip.