TAIPEI, Taiwan In the race to claim technology bragging rights at the 0.13-micron node, Taiwan's two main foundries are betting on different approaches with low-k dielectric materials to boost the performance of integrated chips, especially system-on-chip designs.
Although Taiwan Semiconductor Manufacturing Co. (TSMC) has remained relatively low-key about its use of low-k materials, its rival, United Microelectronics Co. (UMC), has repeatedly touted the advantages of its "true" low-k process. Yet while TSMC and UMC differ on their choice of low-k dielectric materials and processes, it remains unclear which will have the greater edge.
TSMC is using a more traditional chemical vapor deposition (CVD) approach with a thin-film material from Applied Materials Inc. called Black Diamond, which has a k-value of 2.9, in its 0.13-micron copper-based process. UMC is using a spin-on dielectric material from Dow Chemical Co. called SiLK, which has a k-value of 2.7, in its 0.13-micron process.
In terms of RC delay, the difference between 2.7 and 2.9 isn't significant, said Chao Tien-sheng, who researches deep-submicron devices and ultra thin oxides at Taiwan's National Nano Devices Laboratory. But as the foundries ramp up their 0.13-micron production and look toward the 0.10-micron generation, the different low-k processes will likely reveal distinct advantages and disadvantages when considering cost and measuring scalability against reliability of the materials.
Even though its process uses a dielectric with a slightly higher k-value, TSMC believes Applied Materials' films are better suited to dealing with the stress between the dielectric material and copper. "The thermal expansion between your low-k material and copper will be different. The greater the mismatch, the higher the stress," said Chiang Shang-yi, TSMC's senior vice president for R&D. "So if you compare Black Diamond with SiLK, the thermal expansion match with copper is much better with Black Diamond. That is an important consideration. If you choose a better matched one to begin with, it's less likely that the film is going to crack or peel off later."
The complexity of the issues associated with the use of copper and low-k dielectric materials to reduce interconnect and transistor delays spurred UMC into a development partnership with IBM Corp. and Infineon Technologies AG last year. With chip density increasing and layout rules getting tighter, "the inter-metal capacitance copper link is getting very critical for circuit design," said Liou Fu-tai, chief technology officer at UMC.
At 0.18 micron, UMC had been using copper technology as an option, not a baseline, and combined it with transistors having 0.12-micron gate lengths. But the low-k dielectric material used to reduce interconnect delay was a fluorine-doped silicate glass (FSG) with a k-value of 3.6. For the 0.13-micron generation, the goal was a k-value below 3.0 to get the right performance enhancement. "We pushed the low-k dielectric very hard and eventually realized a k-value of 2.7 with SiLK as our base line," Liou said. "If you compare the 2.7 k-value with the 3.5 or 3.6 k-value for the FSG, then you are getting around a 25 percent to 30 percent improvement in RC delay, so this is a significant improvement."
Although the original approach developed by IBM, Infineon and UMC targeted more costly CVD methods, the trio eventually settled on a spin-on dielectric process because they felt it had greater potential for scalability. As k-values approach 2.0, spin-on materials will offer easier routes to performance enhancement, said Tsai Ming-shih, who researches low-k dielectric materials at the nano devices laboratory. "If you use CVD it is difficult to make the material porous. So the SiLK spin-on material has the potential to reduce the capacitance in the future. But there is a trade-off because the spin-on process is unstable compared to the CVD process," Tsai said.
Spin-on materials are more susceptible to cracking, the researchers said, and the organic material within SiLK may contaminate the interconnect, leading to degradation. UMC has acknowledged that problems with spin-on materials, such as thermal stability and mechanical strength, will be "major challenges" as the company advances the technology. But UMC also believes that neither spin-on nor CVD low-k dielectric materials truly satisfy all of the electrical, chemical, mechanical and thermal requirements. "We had to consider the scalability," Liou said. "That was one of the major reasons we switched to spin-on SiLK."
The decision has meant dealing with the inferior strength of the organic material. Under normal conditions, the spin-on dielectric material is too porous to support itself, especially within an eight-layer chip design, Liou said. To strengthen the dielectric layer, UMC is using the barrier metals between copper layers as supporting structures. "In the copper process, we needed to have some isolation layers to prevent copper diffusion," Liou said. "So we can actually utilize the barrier materials to strengthen the dielectric structure."
The three companies are also working through similar roadblocks for the 0.10-micron generation, which UMC plans to introduce into pilot production by the end of next year. TSMC will also move into pilot production at 0.10 micron sometime in the third quarter of next year. Last week, TSMC said it had already finished the design rules of its basic modules for its 0.10-micron process and promised that it would hit a k-value of 2.2, representing about a 20 percent reduction in capacitance.
UMC has been furthering its research of low-k dielectric materials at the 0.10-micron generation for nine months now, and is aiming for a k-value below 2.5 without having to significantly change the materials used. It is posing a challenge for engineers, Liou said, and he cited the gate dielectric material as an example. "The oxide is getting thinner and thinner. At 0.13 micron, the gate oxide for an MPU is already at 16 angstroms so you can imagine that for 0.10 micron it definitely needs to be thinner than this. So we have to work out some novel materials."
As the industry casts its eye even farther along the road map, to sub-0.07-micron processes, Tsai said there are still no clear solutions to improving interconnect performance. "Even copper low-k integration will not be enough. So some other interconnect will have to be applied to such an advanced process, such as an optical interconnect," he said.
At TSMC, the process of striking an acceptable balance with dielectric materials at the 0.10-micron node has already pushed the company through an increasingly labyrinthine process of trial and error. Consequently, TSMC's R&D team has had to work closely with Applied Materials to sort out root causes for weaknesses in Black Diamond and to formulate a recipe that balances issues of physical strength, thermal expansion, fragility and adhesion of the insulator film. "The difference between a physicist and an engineer is that the physicist will . . . try to find out the theory to explain a fact," Chiang said. "But engineers will try to make something work long before they understand it. When we developed this low-k process, we made it work long before we understood everything. So it's an ongoing process."