The timing margin is the time that the data eye is valid for a device to detect a 1 or a 0. It must exist for an interface to work properly. In order for the timing margin to be positive, a high-frequency response is important, even at lower speeds such as 622 MHz. The timing margin is equal to the clock period T (period) minus the following factors:
- T (setup and hold): the sum of the minimum setup and hold times required to detect data (i.e., to resolve a 0 from a 1). The setup time is defined as positive before the falling edge of the clock. The hold time is defined as positive after the falling edge.
- T (rise/fall): the average time between the 20 percent and 80 percent points of the clock signal.
- T (duty cycle): the duty-cycle variation of the clock. This reduces the timing margin if the ASIC clocks the data out upon the rising edge. It can be avoided if the ASIC clock is differential and the clock polarity between the ASIC and mux are swapped.
- T (data skew): the timing variations between data signals from a device.
- T (trace skew): the timing difference caused by the different trace lengths of all the data and clock signals on a pc board.
- T (prop variations): timing variations between the input clock and the output data signals from a device.
- T (jitter): clock jitter, including jitter caused by data intersymbol interference.