DENVERDespite the gold to be found in portable systems that mix communications and computing functions, the U.S. electronics industry is not moving fast enough to adopt the packaging technologies needed to build these thin, lightweight systems, participants said at the HD (high-density) International technical conference here.
And as U.S. companies, already handicapped by the lack of a domestic consumer electronics industry, increasingly turn to contract manufacturers, their ability to integrate advanced packaging technologies may fall further behind, said Leonard Schaper, director of the high-density electronics center at the University of Arkansas.
The worldwide industry is moving on several fronts to increase the density of electronic systems. For example, the direct-chip-attach technology pioneered by IBM Corp. in the 1960s is maturing and moving out to the merchant market.
In the wake of last year's microvia substrate shortage, prices are declining this year for both ceramic and laminate substrates. Bare dice are increasingly available, and more companies are learning to build microvias in a multichip module.
Several companies reported progress in the integration of passive components to a flexible substrate at the HD International conference, co-sponsored by the International Microelectronics and Packaging Society and CMP Media Inc., the publisher of EE Times.
And the most advanced companies are researching ways to stack several substrate layers, building a system layer by layer with flexible batteries, active and passive components, solar cells, sensors and antennae, said Schaper, who spent a dozen years at Bell Labs before joining the Arkansas packaging program. Each layer can be built and tested before it is attached to the succeeding one.
But the U.S. industry could easily fall behind. "Because we gave up on the consumer business, the U.S. industry by and large doesn't have the high-volume products that the Japanese do," Schaper said.
Moreover, the trend toward outsourcing is likely to make it more difficult to integrate cutting-edge system-packaging technologies. Contract manufacturers, for the most part, focus on cost and quality, not system density, a phenomenon Schaper called a "lowest common denominator" effect.
Tom Swirbel, a Motorola engineer, said cell phone manufacturers might gain space and cost savings by using small modules to directly attach the digital baseband IC and memories. As those ICs become more complex, with finer-pitch interconnect, it is more efficient to use a module that can be attached to a lower-density substrate, rather than the potentially more costly approach of building of all the components on a multilayer pc board, Swirbel said.
Multichip packages also are set to move beyond cell phones. To date, combining a static RAM and a flash-memory chip by means of wire bonding within the package has saved some space. A Taiwanese company, APack Technologies Inc., is set to offer a direct-attach technology, licensed from Lucent Technologies, that would connect two or more die by solder bumps. APack began offering a foundry-type packaging service last year, with fine-pitch solder-bump technology as its forte.
The direct approach
Chief technology officer Albert Lin said APack is the first company to offer direct-attach multichip packages, starting with the SRAM-plus-flash combination pioneered by several Japanese companies. APack will work with the Japanese trading house Itochu to acquire flash memories and SRAMs from several vendors, and to create a flip-chip-on-chip stacked package, Lin said. A direct-attach approach yields a 10 percent space savings, he said, with 60 solder bumps between the two chips. The cost is equivalent to that of inner-lead wire bonding, he said.
The first offering is an SRAM-flash stacked combo, initially a 16-Mbit flash and a 2-Mbit SRAM. The company promises those densities will double later this year. And APack says another customer will combine a graphics processor beside two SDRAMs on a module that is tested and packaged as a single chip.
That minimodule will use a bump pitch of 500 microns in a 400-pin ball grid array package, and Lin said it is a lower-cost alternative to embedded DRAM. Other combinations include a DSP with two SRAMs, and an FPGA with flash.
Cost is not the only reason to use multichip packages, Lin said. "For combining mixed-signal technologies, for example, the short connections provide for lower parasitic capacitance and improved inductance."
Stacking chips vertically can create very high-density memory subsystems, but thinning the die thus far has relied on grinding, lapping and other mechanical techniques to remove silicon from the backside of the wafer. That often results in small cracks in the silicon, a more critical problem as the silicon is thinned below 250 microns.
Tru-Si Technologies (Sunnyvale, Calif.) has developed a gas etcher that thins the wafer through fluorine etch, rather than mechanical means, reportedly with no damage to the silicon. The technique creates a thermal reaction to burn away the excess silicon without damaging the gate oxide or aluminum wiring, said Ed Korczynski, director of marketing.
The fluorine-based etcher can remove 100 microns of silicon in about 15 minutes, he said, processing ten to twenty 200-mm wafers an hour.
Thinned silicon is flexible and difficult to handle. Tru-Si has devised an ingenious way of suspending the wafer to compensate. Nitrogen gas is forced through a small chute into a circular opening, creating what the company calls a "minitornado" at the surface of the wafer. The low- and high-pressure areas in the center and along the edges of the twister create a dynamic equilibrium, holding the wafers some 300 microns below the surface of the nitrogen spouts.
Tru-Si's initial system is set to ship in about a month to an unnamed customer. At Semicon West in July, the company is expected to announce wafer-handling technology that will make it feasible to move thinned wafers through the rest of the packaging steps. Lin, at APack, said his company is considering buying a Tru-Si etcher, but needs the wafer-handling capabilities as well. Tru-Si also intends to use its etcher to create openings through the silicon for interconnect purposes.
Bob Graber, senior staff engineer at the Jet Propulsion Laboratory (Pasadena, Calif.), said thinned silicon and through-silicon interconnect have great appeal. "We need the highest-performing interconnect we can get" for chip-to-chip signals, he said. Through-silicon interconnect would enable stacked SRAM-based modules, which would allow the camera to more quickly process an image of a planet's surface and send it back to earth.
Schaper said the technology to thin silicon has important implications for flexible packaging; the University of Arkansas is working with industrial partners to investigate thin-film packages on flexible substrates.
"Thinning the silicon can provide tremendous advantages-we can have very dense chip-scale packages 30 mils thick," he said. "A 50-times savings in space is not unobtainable. Adding passives to a flexible substrate could provide an even greater space savings.
"We need some significant advances in system CAD to get to the point where the system becomes the package."