As RapidIO gains widespread acceptance in the market, discussion surrounding this new high-speed Internet architecture is shifting from, What is RapidIO? to, Does it have what it takes to become the dominant next-generation I/O technology?
We believe RapidIO will emerge as the leading interconnect architecture addressing the ever-growing demand for higher-performance networking equipment. The RapidIO interconnect is targeted primarily at the networking market. Unlike other contemporary computer-centric interconnects, RapidIO addresses the networking industry's need for software transparency, greater reliability, low cost and power, and higher bandwidth in an "in-the-box interconnect." RapidIO provides higher bus speeds that allow chip-to-chip and board-to-board communications at performance levels scaling greater than 64 Gbits/second, with deterministic latency.
In addition, RapidIO has been developed through a cooperative effort involving networking-industry giants such as Alcatel, Cisco Systems, Lucent Technologies, Motorola and Nortel Networks. Many members of the RapidIO Trade Association, formed to direct development of the architecture, believe that network equipment manufacturers, in cooperation with silicon suppliers, must drive interconnection switching standards.
To establish itself, RapidIO first needs to address communications infrastructure vendors. Such vendors typically develop their own proprietary interconnect systems. Second, RapidIO needs to address the needs of those looking for contemporary computer-centric (or server-centric) interconnects.
Faced with increasing time-to-market pressure driven by shorter product release cycles and ever-growing demand for high-performance bandwidth, communications equipment vendors will likely determine that the development time and cost of custom proprietary buses makes this option untenable. As a result, vendors will seek an open-standard interconnect that aligns with their programs' schedules and requirements, allows for continued use of hardware and software legacy equipment, and supports technology evolution.
In a move to demonstrate how RapidIO can meet these needs, the RapidIO Trade Association was established last June. The association is a nonprofit corporation controlled by its members (Tundra is a founding member). The members are major communications infrastructure vendors, and their participation underscores why RapidIO is poised to become the dominant next-generation I/O technology. The philosophy behind the design of RapidIO is "by the customer, for the customer." RapidIO semiconductor and systems suppliers cooperated in developing the architecture to provide the networking industry with the key features it requires for a wide variety of communications applications.
The RapidIO Trade Association directs the future development and drives the adoption of the RapidIO architecture through activities such as public information meetings, conference presentations, technical and marketing working groups, and a comprehensive Web site featuring tutorials, white papers and member discussions. The association's market-leading participants provide an open, community-oriented discussion framework. Industry has responded positively to the association's efforts. RapidIO is increasingly featured in the industry trade media, and the association's public awareness campaign has been well-received.
The RapidIO architecture is a high-performance, packet-switched interconnect technology that addresses the high-performance embedded industry's need for reliability, increased bandwidth and faster bus speeds in an intrasystem interconnect. It allows for chip-to-chip, board-to-board communications at performance levels scaling to 64 Gbits/s. RapidIO is designed to be compatible with the most popular integrated communications processors, host processors and networking digital signal processors. Industry leaders in networking, communications, semiconductors and embedded systems founded the RapidIO Trade Association to develop and support this new open standard.
The RapidIO interconnect is designed to provide 10-Gbit/s aggregate device bandwidth using just 8-bit-wide input and output data ports. The low-voltage differential-signaling (LVDS) technology used by the RapidIO interconnect is capable of scaling to multigigahertz speeds. The port width can span 4 to 16 bits, and future definitions require only physical-layer spec changes, without affecting the logical or transport layers, thus preserving legacy.
Also, high frequency and low packet overhead provide a much narrower interconnect that still offers comparable latency to bus technologies such as PCI and PCI-X. RapidIO supports all needed microprocessor and I/O transactions, is transparent to existing applications and operating system software, and provides a flexible method for memory-mapping systems.
The RapidIO interconnect can recover from all single-bit errors and most multibit errors with no software or higher-level system intervention. It can detect and notify software in the event of more severe errors in order to redirect traffic around failed devices in high-reliability applications. RapidIO was designed to have a minimum silicon footprint for low-cost, full-custom ASIC- or FPGA-based designs-an important aspect of the specification for embedded network and telecom applications. The logic required to implement a RapidIO endpoint is similar in scale to that needed for a PCI endpoint.
Designed for common 0.25- and 0.18-micron CMOS technology, the standard specifies the use of LVDS drivers and receivers, which have been standardized in the industry through IEEE. LVDS driver technology is commonly available on standard ASIC and FPGA offerings.
The standard provides full-duplex communications among devices and targets transmission distances up to 30 inches over standard printed-circuit-board traces.
Hardware-supported symmetric multiprocessing is provided through an optional distributed shared-memory extension. Distributed shared memory is used pervasively in the computer-workstation and server markets, and is becoming more popular in high-performance embedded applications. Distributed shared memory is also useful for maintaining cache coherency for a single processor in systems with distributed-memory controllers. It also supports topologies such as star, linked star and mesh.
There are two RapidIO features that are particularly compelling: its software transparency, and its small silicon footprint and use of widely available process and I/O technologies.
RapidIO technology is transparent to the existing software base, making software development independent of the RapidIO interconnect architecture. To software, the RapidIO interconnect can look just like a traditional microprocessor and peripheral bus.
RapidIO technology also bridges easily to PCI and PCI-X. These features allow users to mix legacy software and PCI chips with RapidIO chips, with no need for special device drivers. Contemporary alternative protocols are message-passing, and thus dependent on operating systems. This means that systems containing the interconnect will require both the new interconnect and the OS software drivers to be updated before the overall system can be sold.
Developers of these alternative protocols are also required to develop third-party relationships with the software vendors, which can involve significant, and possibly difficult, coordination. RapidIO, however, does not require that hardware be dependent on software. In addition, software transparency allows legacy applications to be used in the new system without having to make changes to the applications. For these reasons, software transparency is a distinct advantage of RapidIO.
In terms of its small silicon footprint and widely available process and I/O technologies, RapidIO is designed to be highly accessible to the industry, residing in the sweet spot of the technology and cost curve. Currently, only bleeding-edge semiconductor suppliers can provide some of the exotic I/O and process technologies required by a number of the alternative interconnects.
Since most of the industry consists of fabless semiconductor suppliers, support for a new open standard requires that it be accessible to these companies. RapidIO uses easily accessible technologies in terms of process and I/O, and is designed to have a minimum silicon footprint for low-cost, customer-owned tooling, ASIC- or FPGA-based designs. This use of widely available technology also enables quick time-to-market and innovation in the technology's application.
Developing proprietary interconnects is no longer a viable option for communications equipment vendors, when faced with increasing time-to-market pressure fueled by ever-growing demand for high-performance bandwidth. RapidIO is designed to be affordable and accessible to the industry, using common technology as a base. Competing interconnects are ill-suited to the communications industry due to feature trade-offs made to suit the industry they were designed for.
Looking forward, RapidIO has a partitioned architecture that can be enhanced further as networking requirements evolve over time. Its future development will focus on developing interconnect products to meet the needs of the networking industry.
The RapidIO technology is uniquely optimized for intrasystem interconnections. The combination of performance, ease of use and small silicon footprint paves the path for this new architecture to augment the traditional buses in embedded systems.