For the past several years, bridged hierarchies of buses have been used to connect processors and peripherals on circuit boards-Peripheral Component Interface (PCI) is a good example. But the system performance provided by such hierarchies has little room to grow, and every modification presents additional design problems. For example, widening the bus increases skew, which in turn reduces the maximum possible frequency; more pins are needed for additional signals, resulting in higher costs.
The demands of present and future systems call for a new interconnect that can handle more devices with better performance and fewer pins. Designers need a flexible interconnect architecture that is able to grow and evolve along with the systems it serves. Just as important, this interconnect must be able to work with legacy hardware and software.
One that is being developed is the RapidIO interconnect architecture. It is a point-to-point packet-switched interconnect technology developed by Motorola and Mercury Computer Systems that is targeted primarily at networking, communications and high-performance embedded markets. It can be used for both chip-to-chip and board-to-board communications and can pass data among microprocessors, DSPs, communications and network processors, system memory and peripheral devices within an embedded system.
In many ways this approach is similar to PCI's. Both are intrasystem architectures, both have low pin counts and both require roughly the same logic to implement an endpoint. So how does RapidIO outperform traditional buses?
The critical difference between RapidIO and PCI is that the former is a switched-interconnect architecture, while the latter is a shared-bus architecture. In a typical system today, a host is attached to various devices through a common set of wires, otherwise known as a bus. In order for any of those devices to communicate they must ask an arbitrator for permission to use the bus as a path for data transmission. Since shared wires are used, only one pair of devices can communicate at a time. Any other devices that want to send or receive data must wait until the arbitrator says the bus is available for another transaction.
However, in a packet-switched system all the devices are connected through a common switch-fabric network. In systems with more than two devices, this means that any two devices can communicate at the same time without being unnecessarily blocked by other devices. Therefore, a higher level of transaction concurrency and greater aggregate system bandwidth is achieved with a switched system. How much greater? RapidIO provides throughput exceeding 60 gigabits per second per device interface compared with less than 10 gigabits per second for an entire bus segment with PCI.
Designers continue to search for ways to allow more devices to communicate without slowing the system. For a synchronous bus like PCI, the upper bounds on frequency are limited to the ability of one device to complete a transaction to another device within a common clock period. This means that the clock to data valid on the transmitting device, the flight time and the setup time in the receiving device must be considered. In order to increase performance in the bused topology, the device and system design is constrained to fewer device loads and shorter routing distances. This limits the overall system scalability.
To increase the clock frequency it is necessary for the transmitter to send a clock with the data, which is known as source synchronous clocking. RapidIO utilizes this to achieve clock periods that are less than the transmission flight time. This allows more scalable system topologies, including the ability to use switches to connect more devices and locate them physically farther apart.
RapidIO designers were able to create an interconnect architecture with a low pin count that operated at high frequencies because of the source synchrony described above. For example, a 64-bit PCI bus features a pin count of approximately 85 pins per interface, excluding power and ground pins. RapidIO has only 40 pins per interface, excluding power and grounds, for an 8-bit data path and only 76 pins for a 16-bit interface. Because of the current mode differential signaling (LVDS) utilized by RapidIO, the number of power and ground pins required for an interface is minimal in contrast to the large number of power and ground signals required for a PCI interface with many single-ended simultaneous switching outputs.
The benefit of the reduced pin count is realized in reduced system costs. The RapidIO LVDS interface has low dynamic switching currents, resulting in lower transient currents and lower overall electromagnetic interference.
One of the biggest performance concerns for intrasystem interconnects is transaction overhead-the bytes sent to complete a transaction. Traditional buses like PCI send a request, wait for it to be acknowledged, send a reply, acknowledge the reply, arbitrate for the next master to use the bus and then send a new request. These turnaround and arbitration cycles add to the overhead. RapidIO utilizes unidirectional full-duplex connections between devices, meaning that the interface can be fully pipelined with many outstanding transactions. Since reply information does not interfere with request information, overhead is lowered.
Essentially, the RapidIO architecture specification is broken down into the logical, transport and physical layers. The logical layer defines the overall protocol and packet formats, including transaction types and data payload sizes. Information necessary to get data from one end point to the other is included in the transport layer. The physical layer provides the device-level interface between two components-this includes the electrical interface, low-level flow control and error-detection definitions. Through the use of that layered specification hierarchy, individual specifications can be modified or even added without disturbing the others. Because of such flexibility, RapidIO is also able to grow and evolve to fit changing demands in the market.
In embedded systems, system reliability is extremely important. Traditional interconnects such as PCI have limited error-detection capability and no mechanism to recover from transmission errors. RapidIO has extensive error detection and recovery mechanisms defined. A variety of error-detection methods are used.
Packet transmission is protected with a combination of error-detecting codes and strictly defined protocol. If a corrupt packet is detected, special control symbols are used to force a retransmission of the packet, thus recovering in hardware from the transmission failure. In fact, a RapidIO interface can recover in hardware from all single-bit and most multiple-bit transient transmission failures.
Software transparency within the system is critical. To software, RapidIO appears as a traditional microprocessor and peripheral bus, so it is compatible with application software, operating system software and legacy bus technologies.
Hardware implementations can hide discovery and error management from software unless a software system elects to participate. The architecture also easily bridges to buses like PCI and PCI-X, enabling the system designer to leverage the rich base of legacy hardware.
RapidIO is being developed and promoted as an open standard by the RapidIO Trade Association, which has signed over 20 member companies since its incorporation earlier this year.