First the bad news: Your voltage regulator may be really fast, but it's still too slow to take on a CPU's switching transients because the capacitors do the tough work. Now some good news: Working within the limitations of the output capacitors, voltage regulator design can be optimized for total voltage containment-a limitation of the range it will go up or down with load currents. We call this deregulation technique Adopt (for Analog Devices' Optimal Positioning Technology).
The technique balances the transient response of the CPU core voltage regulator, the equivalent series resistance (ESR) of the reservoir capacitors and a separate linear regulator to provide optimum voltage levels to a system-even with severe current loads. It offers an especially effective implementation for portable computers.
Optimizing a power supply requires understanding, accepting and making the best of its limitations. In the current generation of microprocessors, the fundamental limitation of the power supply is that aside from the charge available in the output capacitors, it does not keep pace with the microprocessor's demands. Optimization around this limitation produces not only a cost benefit but a load power-consumption benefit as well. But solution providers have failed in the past to recognize the benefits or even accept the limitation. Instead, they sought ways to achieve the fastest possible response time, often involving complex nonlinear loop control that was then marketed as the ultimate solution. But from the speediest of solutions down to the subpar ones, the effective performance in a microprocessor application is nearly the same.
The reason for this is simple. A microprocessor's current slew rate is on the order of well above 100 amps per microsecond. The power supply, with its output filter inductor in the way, is limited to nearly two orders of magnitude below that. So the microprocessor's current can slew from zero to the maximum, or vice versa, before the power supply current can slew its current-even if its response time was instantaneous.
That leaves the output capacitors to handle the job of keeping the microprocessor voltage satisfied while the power supply catches up with the new demand. The physically larger "bulk" capacitors dominate output capacitance, and the most cost-effective of those capacitors are still dominated by an ESR in the frequency range of a power supply's response bandwidth. So, surprisingly, it is this parasitic component that determines the peak-to-peak voltage deviation-not the particular response speed of the power supply and not the particular capacitance value.
Low-value, high-frequency ceramic capacitors must also be used to temper the high-frequency edge of the current slew rate of the bulk capacitors; otherwise the ESL of the bulk capacitors and the traces leading to it will permit an additional voltage spike to occur while the microprocessor current slews from one extreme to the other.
But that's the only job of those capacitors in a cost- or size- optimized solution. Adding enough ceramic capacitors to substantially affect the peak voltage-containment capability of the power supply solution is not optimal.
A simple but accurate approach for determining the peak-to-peak voltage deviation of a power supply in a microprocessor application is to multiply the maximum current rating of the microprocessor by two, add to that the ripple current in the power supply's output inductor and multiply that result by the ESR. For a worst-case design, use the maximum ESR and also add the tolerance of the voltage regulation. It is this total peak-to-peak voltage deviation that will determine whether the microprocessor works or fails. If the voltage goes too high or too low, failure occurs. It doesn't matter how quickly the power supply brings the voltage back within the specified regulation band; it will be too slow.
Most power-supply control-IC providers ignore this unsettling fact, of course. They often advertise a faster transient response than the next guy, along with an ability to meet microprocessor load-transient specifications. The fact is, though, that enough capacitors will accomplish that feat for nearly any reasonable control solution.
It's of no help at all to the PC system designer that manufacturers of microprocessors seldom offer timely, clear or consistent information about power supply specifications. A distinction is often made between a static and a dynamic spec, with the dynamic specification voltage-regulation range used only for a microprocessor load transient and for an undetermined number of microseconds following that event. But a transient is usually ill-defined, and CPU engineers have made it clear that the time allowed for the voltage to recover to the specified static range is an eternity for the processor, which is switching at many megahertz. If the processor functions properly with the voltage allowed during a transient occurrence, it can function at that voltage indefinitely.
It behooves the designer to review the practical and inherent limitations of what the preferred buck conversion topology can achieve and then design accordingly. This rational approach points the power converter designer toward a solution that seems counterintuitive to the notion that a faster transient response will yield better performance.
A particular regulation characteristic is required to prepare the converter for a load transient to either of the two load extremes and to simultaneously exploit the opportunity to use the smallest bank of capacitors. It must position the voltage at the top of the allowed regulation window at no load, allowing for aforementioned tolerances, and it must change the voltage "position" linearly throughout the load range down to the bottom of the window at full load. Given the slew rate limitation of the converter relative to the load slew rate and, effectively, a single regulation window that cannot be violated at any time, the optimum converter design is one that would produce an ideal voltage source with an output resistance equal to the maximum tolerable ESR.
This clarifies at least a portion of the design challenge for this type of application: Voltage positioning must be used. The potential advantages of voltage positioning have long been documented, though no one previously has figured out how to exploit the feature without creating dynamic problems.
Another required characteristic is the ability to create an output voltage offset at no load. Since the output voltage must be positioned at the top (i.e., not the center) of the net static regulation window at no load, the implication is that we can't create a voltage feedback loop which regulates at the nominal output voltage and simply use passive voltage positioning (a "droop" resistor in series with the converter output).
A final attribute that must characterize the response of the power converter is the ability to "stick the landing." That is, after a load transient has occurred, the output voltage must remain where it landed immediately after the transient. The voltage positioning must be a full-bandwidth-not simply a dc-characteristic. This is the least understood and most neglected attribute of what is required.
These three characteristics can be realized in Analog Devices' ADP3157 product family for desktop PCs and the ADP3421 for notebook PCs. The ADP3157 family uses only three components and a fixed off-time control. Although the control is not the fastest possible, it is sufficient for the most cost-effective desktop microprocessor voltage-converter solution. For notebooks, which use a smaller bulk capacitor, the ADP3421 implements the fastest-possible topology-an amplifier-free mixed-mode ripple regulator control-for speedy response time. But controlling speed alone is not a complete problem solver. The ADP3421 can be tuned to provide the optimum response characteristic as well.
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