Transistor-precision design"design of analog, mixed-signal and custom integrated circuits"is not easy. The traditional methodology is a very manual, iterative process of an engineer repeating lengthy simulations to determine device variables (such as transistor lengths, transistor widths, resistances, etc.) for topology selection, and achieving performance specifications under nominal and worst case manufacturing and environmental variations. Examples of worst-case manufacturing and environmental variations could include variations in temperature, load, manufacturing process, supply voltage, etc. Furthermore, determining the device variables to meet performance specifications, the designer must constantly juggle tradeoffs. For example, he can improve the bandwidth of the circuit at the expense of power and area, or conversely improve power and area and the expense of bandwidth. Figure 1 illustrates this traditional methodology.
Figure 1: Traditional analog, mixed-signal and custom IC design methodology.
Recently, the front-end design methodology has benefited from tools facilitating designer-controlled automation. One example: Analog Design Automation Inc.'s (ADA) (http://www. analogda.com) Genius high-capacity optimization and performance tradeoff exploration tools aim to eliminate manual iterations with the circuit simulator. High-capacity optimization tools automate the interactions with the simulator. ADA's tools are capable of juggling approximately 1 to 200 device variables, 1 to 30 performance specifications and 1 to 60 manufacturing environmental variations.
These tools output numerous circuit solutions depicting performance tradeoffs of circuits. Using the performance tradeoff exploration tools, the designer is able to visually understand performance tradeoffs and select the design most appropriate for his application. Figure 2 contrasts the traditional design methodology with a designer-controlled automated methodology using the Creative Genius and IP Explorer optimization and performance tradeoff exploration tools.
Figure 2: A Designer-Controlled Automated Methodology merges multiple design explorations into a single flow.
It is important that the high-capacity optimization tools work within the designer's current design flow. The high-capacity optimization tools can input schematics from the design environment (e.g., Cadence Analog Design Environment, Mentor Graphics Design Architect IC, Synopsys Cosmos), and automatically iterate with the designer's trusted simulator (e.g., Cadence Spectre, Mentor Graphics Eldo, Synopsys Hspice). After the designer visualizes the performance tradeoffs and selects the circuit most appropriate for the current application, the device variables are back annotated into the circuit schematic, ready for layout. Figure 3 shows high-capacity optimization tools integrated within the current analog design environment.
Figure 3: High capacity optimization tools integrated within current analog design environment.
These high-capacity optimization and performance tradeoff exploration tools were being used in a commercial tapeout for ControlNet Inc.'s IEEE 1394 PHY design. ControlNet Inc. (http://www. controlnet.com) is a developer of chip cores, circuit designs and software for local and wide-area networking markets. Founded in 1996, the rapidly growing company currently handles complex ASIC/FPGA designs, embedded software solutions and design solutions.
In early 2000, ControlNet broadened its focus to include the FireWire market. The first design for this was a million-gate chip with an eight-port Physical Layer (PHY) analog component. To facilitate the development of this chip, ControlNet put together an analog team, some of whom were remote, to develop an appropriate design that would meet IEEE 1394 specifications.
Under Vice President of Engineering Mark Knecht, the team used the traditional design methodology described in Figure 1 to develop an analog design and taped it out in August 2001. Figure 4 shows a driver circuit test benches and block design in the Cadence Analog Design Environment schematic capture tool (note: the actual Control- Net design is not shown due to confidentiality). After the design was taped out, it became evident that design problems would prevent the chip from meeting the required performance specifications.
Figure 4: Circuit block and test benches shown in Cadence Analog Design environment.
The traditional design approach had resulted in one block meeting standards, but two blocks that failed. The company's original bandgap reference had trouble meeting required gain, temperature coefficient and output voltage requirements, and its data receiver block was unable to switch at the proper frequency over all manufacturing and environmental corners. The goal was to tape out a design robust to manufacturing and environmental variations that met specifications with a high level of confidence of functionality.
The problem for ControlNet was that its engineering staff could not run enough manufacturing and environmental variation simulations by hand to properly analyze all the circuits. The attempted runs proved to be excessively tedious and time consuming tasks.
Optimization tools to the rescue
The ADA Genius tools were first used to determine whether the basic architecture would meet the specs. Following that initial assessment, the ControlNet team could then evaluate all the manufacturing and environmental variations. Creative Genius was used to run an initial analysis on the bandgap reference design with the original 52 design device variables under nominal conditions and under three worst-case manufacturing and environmental variations (Figure 5) conditions. The automated circuit optimization tool within Creative Genius resized each of the 26 components and produced a library of comparable circuit solutions.
Figure 5: IP Explorer screenshot showing circuit performance tradeoffs.
At this point, IP Explorer, ADA's multi-dimensional performance tradeoff exploration tool, allowed designers to see the performance tradeoffs within each optimized circuit. Designers were then able to carefully weigh performance tradeoffs and select the most robust design for the application.
Each of the vertical axes in Figure 5 depicts a performance specification, and each line segment across the screen shows a particular circuit. The "ideal" circuit that is top performing for each of the performance objectives would be a line segment across the top of the vertical axes. However, since there are tradeoffs, the designer is able to see the relative positive and negative attributes of each candidate design, and compared with the designer's original circuit shown in orange.
For this circuit topology, the optimization tool discovered some interesting performance tradeoffs. For example, the designer could choose a design with better unity gain bandwidth and area if he is willing to compromise supply current. However, if he desires the circuit with superior supply current, he must sacrifice unity gain bandwidth and area. The designer is able to narrow down the solution choices to the circuit with the most appropriate tradeoffs for this IEEE 1394 PHY design.
As shown in Figure 6, the designer chose a circuit generated by Creative Genius which slightly worsened the phase margin (PM) of his original circuit to make drastic improvements in other specifications.
Figure 6: Designer's chosen circuit based on performance tradeoffs.
Using the optimization tools, maximum op-amp gain increased from 41.3 dB to 119.5 dB at 750 mV common-mode input; the temperature coefficient decreased from 403.88 to 24.33 ppm/C; and the overall voltage output variation decreased from 0.02 to 0.0025 V. Manual efforts would have never produced the necessary sizings, ControlNet believes.
A similar procedure was run on the output common-mode voltage driver to quickly evaluate the circuit under 16 worst-case design corners. A designer built the appropriate testbenches and worst-case analysis for the 26- transistor/13 specification design. ADA's tool then verified that the design would work under variations in temperature variation, power supply voltage variation, cable capacitance, variation and process corner variations.
The 256-corner data receiver block proved be the most challenging circuit. ControlNet had multiple problems trying to validate the design manually through a worst-case analysis over corners, and the design failed to meet more stringent design goals. It could not switch over all corners at a frequency of 400 MHz and an input signal amplitude of 70mV, however the designers were concerned that they were missing the solution. The optimization was used in this case optimize the circuit so that it would meet the worst corners for test bench simulations. By optimizing with automated tools, this complex redesign was able to meet IEEE standards.
Using Creative Genius and IP Explorer high capacity optimization and performance tradeoff exploration tools, ControlNet was able to:
Utilize a structured design methodology that allows designers to be quickly added to a team or project by simply learning the methodology
Determine the performance limits of a given topology
Comprehensively evaluate circuit performance across multiple corners
Generate a library of optimized circuits for a given topology
Better communicate the strengths of each design and the efforts of design teams --