High speed backplane design is usually an iterative process. Tradeoffs must be made among multiple conflicting goals and constraints including:
* Backplane architecture - desired vs. achievable logical and physical configuration.
* Electrical behavior - signal integrity and performance, power and ground currents.
* Electrical design - dielectric materials, dielectric thickness, trace geometry, stackup.
* Fabrication constraints - panel size, fabrication processes and tolerances.
* Connectors " performance, size, signal density, durability.
* Design flow " total number of connections, design tools, design verification.
* Testing " DC continuity and isolation, AC performance, testability.
* Regulatory compliance " electrical, environmental, fire resistance.
* Cost " development, manufacturing, test.
* Schedule " feasibility, modeling, design, fabrication, testing, mistakes, redesign.
The wide variety of conflicting constraints explains why very few large scale backplane design projects are successfully completed in a single pass. Basically, there is no such thing as a cheap, large, high speed, high density backplane " compromises are unavoidable and the choices are not easy or obvious.
In the remainder of this paper we will discuss some of these design challenges in greater detail. Clearly a comprehensive treatment would be a book rather than a paper.
Before commencing detailed design of a large high speed backplane it is wise to consider the feasibility of the backplane architecture. Usually the original architecture must be progressively refined until it can actually be built.
Increasing backplane bandwidth requires increasing the number of signals and/or the speed of the individual signals. High speed signals generally use differential transmission lines. To achieve very low bit error rates (BER) high frequency signal scattering and dispersion must be carefully controlled, as well as crosstalk and interactions between AC ground references and DC power and ground currents.
Transmitting higher frequencies over longer distances using conventional design approaches requires wider signal traces to reduce high frequency attenuation. Wider signal traces require thicker dielectric layers and/or higher performance dielectric materials to maintain impedance match and reduce frequency-dependent attenuation. Increasing either trace width or dielectric thickness reduces the routing density. Increasing the separation between differential trace pairs reduces crosstalk but also reduces routing density. The need to isolate AC ground references from DC power and ground currents tends to add more layers and therefore greater thickness. The total number of conductive layers can easily reach 20, 30 or higher.
Common panels do not exceed 18 to 24 inches (50 to 60 cm) in the longest dimension, however large panels can reach 30 to 40 inches (75 to 100 cm) which may exceed the capabilities of most manufacturing and test equipment. The feasibility of reducing trace geometry or increasing the number of layers and/or the dielectric thickness to improve routability and signal integrity is limited by the fabrication process. Process limitations include tolerances for etching, lamination and drilling.
High speed drilling works well for panel thickness up to 0.30 or 0.35 inches (7 or 8 mm), however larger drill diameters are required for deeper holes Typical drill aspect ratio (depth to diameter ratio) limitations range between 8:1 and 12:1. Thicker panels require multiple drill passes which results in decreased drilling accuracy. Larger vias and multiple drill passes each degrade the high frequency performance of the finished holes. Registration errors in etching, lamination and drilling degrade signal integrity and process yield at small feature sizes.
High performance connectors must have very good impedance matching to reduce reflections, and very good shielding to minimize crosstalk. Common high performance backplane connectors have 40 to 60 differential pairs per lineal inch (16 to 24 pairs per cm). Common connector lengths (per row) range from under 4 inches (10 cm) to over 12 inches (30 cm). So the total number of differential pairs per connector row can range from under 200 to over 1,000. Typically there is one ground connection per differential pair, giving a total pin count per row from under 600 to over 3,000. Very high signal density connectors reduce daughter card size but they increase routing congestion inside the backplane.
Not all high performance connectors are good backplane connectors because backplane connectors must be able to withstand multiple blind insertion/removal cycles. Most backplane connectors use press-fit pins, which combine durability with easy assembly and replacement. The disadvantage of press-fit pins is that they dictate the hole locations and geometry, which may not be optimal for signal integrity or routing. A few backplane connectors use surface mount technology, which may allow greater freedom in hole location and geometry. The disadvantages of surface mount connectors include more difficult assembly and replacement, and in some cases impaired durability.
Common daughter card spacing is 0.8 to 1.2 inches (2 to 3 cm). Typical backplanes can accommodate 8 to 12 daughter cards, however large backplanes may need to accommodate 24 to 32 daughter cards. With 200 to 1,000 differential pairs per daughter card the number of differential terminations in a backplane can range from under 2,000 to over 32,000, giving a total pin count per backplane from under 6,000 to over 96,000. Since high speed differential transmissions lines are usually point-to-point connections the total number of differential connections can range from under 1,000 to over 16,000, giving a total net count ranging from under 2,000 to over 32,000 (assuming all ground pins are connected to a single net.
Routing density and routability are major issues for large backplanes. Routability can be achieved by adding more signal layers, by increasing the signal density within layers, or by modifying the logical or physical configuration. Higher routing efficiency can be achieved by manual routing because a human can take advantage of architectural knowledge, whereas CAD tools generally operate from flat net lists.
Common PCB CAD tools can readily handle designs with thousands of pins and nets; however many tools encounter problems when confronted with tens of thousands of pins and nets. Problems range from complete inability to capture or load the design, through VERY slow performance even on large workstations, to generation of incomplete output files and spurious error reports. Workarounds will often be necessary.
A full scale 'shakedown cruise' to verify the complete development flow is a good, albeit costly, way to validate assumptions and minimize risk for the real project.
Multilayer printed circuit boards (PCBs) consist of alternating layers of copper foil separated by dielectric materials. There are two kinds of dielectric material " core and prepreg. Cores are firmer dielectric layers clad with copper foil on one or both sides. Two layers of circuit patterns are etched from the copper foil on opposite sides of a core. For boards with more than two circuit layers multiple cores are used, so there are usually an even number of circuit layers in the finished panel. Prepregs are softer dielectric layers provide buffering and bonding between the core layers. The complete PCB stackup is laminated from alternating dielectric layers of cores and prepregs, with copper foil sandwiched in between.
The sequence of etching, lamination, drilling, hole plating and back drilling for a large backplane can be very complex. Often intermediate sub-assemblies will be fabricated, processed and then combined to produce the final panel.
Each stage in the fabrication process has associated tolerances, many of which manifest themselves as various forms of registration errors. In general the alignment between multiple traces (or pads or other features) on the same foil will be best, the alignment between multiple traces on opposite sides of the same core will not be as good, the alignment between multiple cores of the same sub-assembly will be worse yet, and the alignment between pads and drilled holes will be the least accurate. It is possible to drill very accurate holes through adjacent layers using laser drilling with optical alignment, however only mechanical drilling with mechanical alignment is feasible for deeper holes.
Table 1 shows the properties of some common dielectric materials that can be used for backplanes. This table is by no means complete. " other materials are in use and new materials are being introduced.
Table 1. Properties of common dielectric materials
Selecting dielectric materials for large high performance backplanes involves tradeoffs between cost, size, number of layers, dielectric thickness, high frequency performance and mechanical properties. All dielectric materials represent compromises between cost, electrical properties and mechanical properties. Not surprisingly, the materials that combine the best electrical and mechanical properties tend to be more expensive.
The dielectric constant (?r, epsilon-r) affects the AC impedance of the transmission line. The loss tangent (Tan ???delta) affects the high frequency signal attenuation. Both dielectric constant and loss tangent vary with frequency.
Many high performance dielectric materials are not suitable for large backplanes due to their mechanical properties. Some materials deform excessively during the lamination and drilling processes. Most dielectric materials rely on some kind of glass, ceramic or embedded material for strength and dimensional stability, however these materials may not yield clean enough drill holes at finer tolerances. Some materials are susceptible to delamination under mechanical or thermal stress. Some materials lack sufficient foil peel resistance for surface mount components. And some materials do not meet fire or other safety codes.
The performance of a high frequency transmission line is strongly affected by impedance matching, high frequency attenuation and noise immunity.
It is possible to design a high frequency transmission line using only a single conductor. Nevertheless most high frequency signals use differential transmission lines (i.e. a pair of coupled conductors carrying signals of opposite polarity). Although differential signaling appears wasteful of both pins and signal traces it results in much better noise immunity. Differential signals produce less conducted noise because the opposite power and ground current flows cancel each other both in the line driver and in the transmission line. Differential signals produce less radiated noise because over a modest distance the opposite fields induced by the opposite currents cancel each other. Differential signals are less susceptible to noise because most sources of noise (common mode noise) tend to affect both signal lines identically, producing a variation in common mode voltage but not in differential voltage.