WAYNE, N.J. " Startup Accelerant Networks (Beaverton, Ore.) is expanding its backplane transceiver device family with the release Monday (Oct. 27) of a transceiver the company claims can deliver 10-Gbit links across communications backplanes.
The AN6420 serializer/deserializer (serdes) is a 2:1 multiplexer/demultiplexer that can take in eight binary 3.12-Gbit/s channels on the system side and multiplex them together into four 6.25-Gbit/s, four-level pulse amplitude modulation (PAM4) channels that get sent out over backplanes.
However, Accelerant claims these are conservative estimates. According to Vice President of Marketing Bill Hoppin, Accelerant demonstrated that its AN6420 device's eight system-side channels can operate up to 5 Gbit/s while the four backplane connections have been demonstrated to operate up to 10 Gbit/s, a performance many communication OEMs have been looking to achieve.
While the 10-Gbi/s performance levels have so far been achieved only in demonstrations, Accelerant is guaranteeing is that each channel will deliver true 6.25-Gbit/s performance.
Manufacturers often quote a throughput figure in many transceiver designs. However, when 8B/10B and other encoding schemes are used to send traffic over these links, real link throughput drops. To solve the problem, Accelerant implemented a scrambler and clock-and-data recovery circuitry on the chip to account for encoded streams.
Additionally, the company has built a digital phase-lock loop (DPLL) architecture that it has "sprinkled" in 23 different spots on the chip. "By distributing the DPLL, we can retune the signals all around the chip," Hoppin said.
According to Hoppin, these three elements allow the AN6420 to deliver signals with zero overhead, thus allowing the transceiver to deliver 6.25-Gbit/s links even when dealing with encoded streams. "This is a subtle feature, but it's huge for the design community," Hoppin added.
To further improve channel performance, the AN6420 also comes equipped with two equalization approaches. In scenarios where the AN6420 is linking with a board using a transceiver from another company, the chip relies on its receive section to perform equalization. In this situation, the chip employs a decision feedback technique that makes a decision on the first bit, then a "careful decision" on where the next bit will come from, Hoppin said.
In cases where Accelerants chips are used on both end of the link, the AN6420 uses information received from one end to tell the transmitter in band what to do, Hoppin said. This equaliziation technique provides seven programmable taps, each with their own settings, he added.
Accelerant has also taken steps to reduce board space on the design by integrating all of the system I/O capacitors into the AN6420 package. "It's amazing how much board space this technique saves," Hoppin said,
The AN6420 is developed in a 0.13-micron CMOS process and draws 1 W power during operation. The chip includes a per-channel, programmable bit-error-rate tester as well as a JTAG port for debugging. The chip can operate in synchronous or asynchronous mode, and works in XAUI, Sonet, PCI-X and Fibre channel applications.
Sampling now, the AN9420 is housed in a 17 x 17-mm, 256-ball BGA package and is priced at $80 in volume. Volume production is scheduled for the second quarter of 2004.