WAYNE, N.J. " Agere Systems Inc. has built a 90-nanometer serializer/deserializer chip that can deliver 12.5-Gbit/second throughput, giving designers a way to provide 10-Gbit channels across backplanes in networking-box architectures.
Interest in delivering 10-Gbit/s channels across backplanes is on the rise, but backplane transceivers that could deliver such performance have not been available. "The market hasn't had a 10-Gbit serdes that could drive a backplane," said Robert Brink, high-speed applications manager at Agere Systems (Allentown, Pa.).
After about a year of work, Agere says it has built a test chip that will allow it to create standalone serdes chips or serdes blocks that can be embedded into ASICs to deliver 12.5-Gbit connectivity across a single pair.
Agere's test chip included blocks for testing voltage-controlled oscillator performance, evaluating the entire phase-locked loop function, testing high-speed clock routing channels and evaluating high-speed transmit buffering, Brink said. "Through these blocks we can understand how the serdes will perform without having to build a whole serdes," he said.
Tests indicate the chip can operate either in nonreturn-to-zero or in four-level pulse-amplitude modulation (PAM4) modes, Agere said. The serdes can also meet the jitter and receiver specification laid out in the Fibre Channel, Ethernet, Sonet, PCI Express and SerialATA specs, said Greg Sheets, director of high-speed interconnect at Agere.
Agere expects to have the 90-nm serdes block available for ASICs next summer. The company did not say when a standalone 90-nm serdes chip would be available.