This article introduces the CMOS integrated transceiver circuit EM4095 for RFID applications working with transponders at a frequency of typically 125 kHz. The EM4095 is a single-chip RFID reader IC and is great for applications where board space must be saved. The paper describes the interoperability with a read-only and a read/write transponder in specific examples.
This application note offers a technical overview on the EM4095 and practical design tips. A typical reader circuit setup is shown. The also examines interoperability of the EM4095 with read-only and read/write transponders.
- Integrated PLL system to achieve self adaptive carrier frequency to antenna resonant frequency
- No external quartz required
- 100 kHz to 150 kHz carrier frequency range
- Direct antenna driving using bridge drivers
- Data transmission by OOK (100% Amplitude Modulation) using bridge driver
- Data transmission by Amplitude Modulation with externally adjustable modulation index using single ended driver
- Multiple transponder protocol compatibility (e.g. EM400X, EM4050, EM4150, EM4070, EM4170, EM4069)
- Sleep mode 1µA
- USB compatible power supply range
- -40C to +85C temperature range
- Small outline plastic package SO16 or PSOP2 16
Figure 1: Typical operating configuration for read only mode.
Resonant circuit parameters
In an RFID system where the RF frequency is defined by a resonator there are three variables: (1) the resonant frequency of antenna, (2) the resonant frequency of transponder and (3) the RF driving frequency. Where a PLL is used, there are only two variables, since the resonant frequency of the antenna and the RF driving frequency are the same.
Analysis suggests that, for a system having defined tolerances on the antenna and transponder side, the range where one demodulation chain (AM) with fixed sampling point can be used is much narrower for a PLL system. In fact, taking in account technically achievable tolerances the resonator system using one sampling point is not feasible; two channels with 90-degree shifted sampling points are needed (AM/FM). This leads to more expensive system which is also more complex to operate.
A PLL system with one sampling point has also limitations for the tolerance range of transponder and antenna. As a general rule, the higher the quality factors (Q) of the two resonant circuits are, the tighter tolerances that are required (this is also true for a resonator system).
An RFID system with air transponder coils is normally not problematic. For transponders with a Q lower than 15, a tolerance of ۯ kHz on the antenna and transponder side is acceptable.
Transponders with ferrite core coils have usually higher quality factors (up to 40) and are therefore much more sensitive to tolerance variations.
Figure 2: EM4095 Block Diagram.
The block diagram given in fig. 2 describes the EM4095 architecture. The transmitting section integrates a PLL and a bridge driver that is formed by two push-pull drivers driven by two signals phase shifted 180 degrees. The receiving section contains a synchronous demodulator (sampler) and a filtering chain. The chain achieves a band-pass-filtering function defined by two low-frequency zeroes, depending on capacitors Cdec and Cdc2 and a built-in high frequency pole, in the range of 10kHz.
Board design tips
Reliability of a reader application using the EM4095 transceiver can be optimized following some basic design rules pointed out in this chapter.
Pins DVDD and DVSS should be connected to VDD and VSS respectively. Care should be taken that voltage drops due to driver current which is flowing through pins DVDD and DVSS does not provoke voltage drops on VDD and VSS. The DVSS pin and DVDD pin should be blocked by a 100nF capacitor between the two pins as close as possible to the chip. This should prevent the supply spikes caused by the antenna drivers. Blocking of the analog supply pins VSS and VDD next to the chip is also advisable. Blocking capacitors are not included in the EM4095 application schematics.
All capacitors related to pins DC2, AGND and DMOD_IN should be connected to the same VSS line, which should be connected directly to VSS pin of the chip. This VSS line should not be connected to other elements or be a part of "supply line" going to DVSS.
The interconnecting lines to all the sensitive pins (listed above) must be as short as possible. This is also true for the VSS line to the blocking capacitors. The capacitive coupling from all "hot" lines specially the digital output DEMOD_OUT to the sensitive input pins DEMOD_IN, FCAP, CDEC, DC2 and AGND should be avoided.
EM can provide a sample PCB with EM4095, power supply filter caps and caps on DEMOD_IN, FCAP, CDEC, DC2 and AGND already mounted.
Since antenna drivers (ANT) depend on the level of VDD and VSS, it is clear that all variations and noise in power supply are directly fed to antenna resonant circuit. Any supply variation of antenna high voltage in the mV region will result in reduced functionality or even malfunction of the system (i.e., a transponder signal superimposed on antenna voltage is in the range of tens of mV). Special care has to be taken to filter low frequency noise in range up to 20 kHz since the transponder signal is in this frequency range.
The EM4095 does not limit the current delivered by ANT drivers. The absolute maximum rating on these two outputs is 300 mA. Design of antenna resonant circuit connected to ANT drivers must be done in a way that maximum peak current of 250 mA is never exceeded. Antenna current can be reduced by adding series resistor.
It is recommended to connect MOD to VSS in read-only applications. The EM4095 has some built in test features, which are switched on when SHD and MOD pins are high. It is thus recommended that MOD pin is kept low while SHD is high.
The AGND voltage is filtered by external capacitor and internal resistor of 2kohms. The AGND capacitor can be increased from 220nF up to 1uF. The bigger capacitor value can slightly reduce the receive noise.
Design of the DEMOD_IN capacitive divider
The reception filtering is done in two stages. The first stage zero is defined by external capacitor Cdec and internal resistor (100 kohms). The pole of the first stage is set internally to ~ 25 kHz. The second stage zero is defined by external capacitor Cdc2 and internal resistor. The pole of the second stage is defined internally to 12 kHz.
This means that the reception poles can not be changed and the upper frequencies are limited by two stages filter having -3dB frequencies at 25 kHz and 12 kHz.
The two stage zeroes can be changed.
The capacitor divider should be designed in a way that parasitic capacitances (few pF of DMOD_IN pin, parasitics of PCB, etc.) do not influence divider ratio. A capacitor with a value from 1 to 2 nF is proposed for connection from DMOD_IN pin to VSS (CDV2). A capacitor from antenna high voltage point to DMOD_IN (CDV1) pin is then calculated from divider ratio. Additional capacitance of capacitive divider must be compensated by accordingly smaller resonant capacitor.
The default settings should be at about Cdec = 100nF and Cdc2 = 10nF. This combination is more than sufficient to satisfy the sensitivity specification and to enable reliable operation.
Increasing the Cdc2 capacitor (max. 22 nF) will in real application increase the receive sensitivity, specially if the Q of the transponder is high, which causes non-rectangular (sloped) receive input signal.
Increasing the Cdc2 capacitor will increase the receive bandwidth what in consequence increases the receive gain for sloped signals.
The advisable range for Cdc2 is from 6.8 nF to 22nF and Cdec from 33 nF to 220 nF. A higher capacitor value can increase the start-up time.
Calculating an example
The following example presents the EM4095 front-end using on-off-keying (OOK) communication protocol from the reader to transponder (uplink). Some helpful equations are presented here. They can be used for principal design, but the calculations have to be verified by measurement. Eventually the results have to be adjusted to compensate possible parasitics and second order effects.
A reader system with a high Q antenna will be specified. The system will operate at
f0 = 125 kHz
To design a low cost read/write (R/W) basestation using OOK communication protocol for the uplink communication, the "Typical Operating Configuration" (figure1) is used.
The antenna inductivity is usually chosen from within the range from 300 uH to 800 uH. In this example the following inductivity and quality factor have been selected
LA = 725 uH ± 1 percent
QA = 40.
The ohmic antenna resistance can be found by applying the formula
RANT = 14.23 ohms
The antenna driver resistance and the power supply voltage of
RAD = 3 ohms
VDD - VSS = 5V
will be used in following calculations.
System will operate at 125 kHz. The resonant capacitor CRES is calculated by
CRES = 2.24 nF
Remark: Until this point of the calculation, Cdv1 and Cdv2 effect (the real resonant frequency value) has been neglected, as they are not yet calculated.
Calculate the reader antenna current and voltage by the given antenna driven in the bridge-driver configuration and applying the equations
the current and the voltage at the reader antenna are (Rser=0):
IANT(peak) = 315 mA
VANT(peak) = 182 V
To suite the maximum specifications at DEMOD_IN, the antenna voltage would have to be divided by nearly a factor of
dC = 100.
Decimating the antenna voltage ensures a proper demodulation of the received transponder data signal.
Applying a serial resistor RSER to the resonance circuit can reduce the division factor dc.
Reader antenna quality factor
Practical antenna circuit Q factors, in case full receiver chain is used, can be found between 10 and 15. Introducing a serial resistor RSER, will limit the high voltage by reducing the overall quality factor, without reducing reading distance. In other words, the resonance circuit quality factor Q can be reduced by adding a serial resistor RSER.
Reduced Q also improves recovery time after modulation, which is especially important for transponders with data rates at 32 and 40 periods per bit. Furthermore a lower antenna current will limit the junction temperature of the chip.
The following calculations are based on a serial resistor of
RSER = 33 ohms
which has been calculated iteratively by using the equations.
The resulting antenna current and voltage in resonance are more suitable
IANT(peak)= 119.59 mA,
VANT(peak) = 69.22 V.