Many existing Ethernet devices are being converted from wall adapter power sources to utilize the newly-released 802.3af Power over Ethernet standard. With a wall adapter, power system efficiency was not as much of an issue " but PoE changes that.
This article helps the designer determine how much power is available when operating from a PoE source. A simple power-topology modeling technique will assist the designer in optimizing their design. An example in which "bolting" a PoE front end onto an existing design results in only 8.1W available, while redesigning results in 10.4W available to the application.
Power Loss - A lot of Little Leaks
Unfortunately, the power losses are made up of a lot of "small" contributors. The first step is to revisit how much power is really available before processing it into application power.
Figure 1 shows a basic block diagram of the PSE interconnection through the DC/DC converter and application circuits. The calculations in Table 1 assume that the PSE output (44V min) is connected through 20Ω of cable into a PD. The PD front end has a transformer (1Ω total, 0.5Ω each side to the center-tap), a full wave bridge, and a hot-swap controller with a 1Ω switch (FET) in series.
Figure 1 - Basic PoE Power Block Diagram.
Table 1 - Analysis of PoE Distribution and Front End Losses.
The 802.3af standard defines the 2.45W worst case cable loss. The input diode bridge dominates the additional front-end losses of .78W.
In the simplest case, a single output 3.3V converter at 90 percent efficiency will yield an available output power of (0.9 * 12.16) 10.9W. Although the 90 percent efficiency may be viewed as optimistic, it provides a reasonable baseline.
Next, estimate the output power available from a more complex power supply. A simple modeling technique is used to study the effect of topology and technology for each regulator on output power. Output voltages of +5V @ .2A, 3.3V @2A, 2.5V @ .25A, and 1.8V @ .25A have been arbitrarily assumed. These add up to a reasonable 9.6W.
The following two diagrams show two possible supply architectures and technology choices. The first topology assumes that an existing appliance design that had a 12V wall adapter was re-used, simply replacing the adapter with a 48V to 12 V front end. The second design attempts to maximize the available power.
Figure 2 - Alternative Supply Topologies.
The modeling technique starts at the right-most regulators, calculating their loss, and adding their input power to the output of the previous stage. Simplifying assumptions of 90 percent efficiency for a switcher and no bias current for a linear regulator were made. For the 48V to 3.3V converter, this corresponds to a pretty good synchronous output rectifier circuit. To compare the effect of a diode output, an 85 percent efficiency case was compared. These assumptions do a good job to a first order of magnitude; they can always be adjusted based on an actual design or the judgment of the individual. This modeling technique is easily implemented in Excel.
Rather than solving a lot of simultaneous equations, the "bulk" output current (3.3V) was adjusted to achieve an input power that matched the 12.16W calculated above.
Table 2 - Topology Models.
Topology 1's first stage output power (10.94W) was calculated as the sum of output I*V + Losses. Then the input power (12.16W) was calculated as (output power / efficiency). The 3.3V output current was adjusted until the 12V stage input power was about the 12.16W calculated above. For each regulator, the output current indicated is what the load receives. The actual regulator current is higher; the 2.5V regulator supplies both 0.25A out plus 0.25A into the 1.8V regulator for a total of 0.5A. A similar process was used for Topology 2.
The conclusions for this contrived application are quite startling. Re-using the original topology makes only 8.11W available on the output while a redesign makes 10.43W available, an increase of 28 percent. Not using a synchronous rectifier for the 3.3V converter drops the available power by 0.61W.
This modeling technique allows the designer to rapidly calculate available output power based on topology and technology choices. The designer can use this information to trade off available power, complexity, and cost.