The operating data rates of current state-of-the-art backplane serial links are in the 2.5- to 3.125-Gbit/s range. As silicon becomes available that can support higher data rates into the 5- and 10-Gbit/s range, comm system designers are looking for ways to support these higher rates within their existing backplanes.
In the 5- to 10-Gbit/s range, the technical challenges created by phenomenon such as reflections and crosstalk increase. In addition, new voltage- and timing-related challenges have arisen that typically do not exist in lower data rate ranges. These include skin effect, dielectric loss, inter-symbol interference (ISI), and via stub effect.
To overcome these challenges, system designers must develop accurate and efficient models for both the active and the passive components of the system. Silicon vendors also need channel models to successfully design proper on-chip circuits for implementing various techniques like equalization and reflection cancellation. By modeling the known deterministic effects of the channel, signal-integrity related problems can be understood, and techniques can be developed to minimize their impacts.
To develop a backplane model, individual models for connectors, packages, PCB traces and vias are needed. In this article, we'll examine the technical challenges that must be overcome to support 5- to 10-Gbit/s rates, and the corresponding channel model requirements.
As the data transfer rate on the channel increases, "old" problems are exacerbated, and "new" problems arise that must be addressed. Figure 1 shows the key timing and voltage related impairments that must be addressed as data rates increase.
Figure 1: Above 3 Gbit/s, backplane transmission becomes a major challenge.
Figure 1 is divided into three regions of interest:
- The 100 Mbit/s to 1 Gbit/s region
- The 1 to 3 Gbit/s region
- The 3 to 10 Gbit/s region
The 100 -bit/s to 1-Git/s region is the better understood of the three. In this range the designer must compensate for the issues listed in the above drawing and remove fixed errors such as impedance mismatch and data/clock skew issues.
In the 1- to 3-Gbit/s range, the designer must make adjustments that are a function of the channel's electrical behavior, such as channel loss and distortion. These quantities are typically not known when the silicon is designed. Consequently, a feedback loop can be used to adjust the variables of concern. For example, the transmit driver output swing driving into a lossy channel can be adjusted by a feedback loop sensing the input swing at the far end receiver. The objective in this example is to overdrive the channel and compensate for its losses.
Above 3 Gbit/s, the existing variables become harder to manage, and new variables begin to emerge as shown in the above drawing. These include skin effect, dielectric loss, intersymbol interference (ISI), via stub effect, ISI jitter, and inter-pair skew. Let's look at these six in more detail starting with skin effect.