System timing and synchronization remains one of the least understood sciences in today's communications equipment design processes. As the essential foundation of all multiplexing, switching and transmission equipment, system timing's importance has been growing as the demands and variety of communications services increase.
System timing encompasses a number of specialized functions common to equipment located from the access network to the core. These can be separated into two basic categories: timing processing and timing distribution.
Figure 1. Basic System-Level NE Synchronization Scheme.
Timing processing involves functions that pertain to network synchronization standards. These functions typically include clock recovery, clock monitoring, clock retiming, holdover/free-run and protection switching. Timing distribution involves functions that pertain to specific system or product requirements. These functions typically include clock synthesis, cross-coupling, phase build-out and fan-out.
Synchronization engineering ensures that both network standards and system requirements are properly incorporated to support robust performance and operation. Otherwise, data loss, missed service level agreements, and loss of service revenue will result.
In a telecommunications network, timing is distributed via a network of stand-alone timing systems called building integrated timing supplies (BITS) or synchronization supply unit (SSU). In North America, the performance and timing signal quality of the BITS is classified by a standardized scheme called stratum levels. Within a communications network, proper synchronization engineering is needed to ensure that this source of timing continues to flow with a constant quality to all network equipment. Within a piece of network equipment, system timing provides sub-assemblies, circuit boards, and components with the timing flows provided by the network.
Figure 2a. Scalable Sub-System Timing: Small NE Architecture.
Figure 2b. Scalable Sub-System Timing: Medium NE Architecture.
Figure 2c. Scalable Sub-System Timing: Large NE Architecture.
At a system level, synchronization engineering must answer questions regarding timing processing and distribution to define the system timing architecture. These have implications on the required timing interfaces, stratum level performance, and timing signal routing. Further, the system fault performance depends on the system timing architecture as well. The ability to tolerate a single fault or multiple simultaneous faults may require redundant functions and a cross-coupling of timing signals between active and mate sides.
When faults occur, hitless-switching to a redundant side may require support of effective clock monitoring, holdover or phase build-out capability. Even recovery from a fault may also require clock monitoring, seamless exit from holdover, or phase-build-out capability. Such system level functionality may be necessary to provide uninterrupted timing clocks during fault and recovery events.
At a sub-system and circuit board level, synchronization engineering is concerned with clock signal distribution, clock types, and protection schemes. When distributing clock signals between subsystems or circuit boards, it is not always practical to run multiple frequencies or clock phases. Rather, a common frequency may be distributed to circuit boards and then "synthesized" to the desired frequency or frequencies at the circuit board by means of a clock synthesizer. Phase compensation to correct the effects of clock skew may be accomplished with a phase build-out function that introduces a constant and pre-set phase offset. Phase offsets are valuable for distributing precise timing over a backplane or large systems.
Sub-systems and circuit boards typically require redundant clock routing to meet carrier grade expectations. Therefore, hitless switching between these redundant clocks is also expected. To do this, the relationship between clock pulses and framing pulses needs to be maintained before, during and after the switch. The bit error rate of a system is impacted when this relationship is not preserved.
Clock distribution at a circuit board level also requires careful engineering and planning. It is not always practical to "star" route clock signals between multiple devices. In addition to routing congestion, "star" routing may serve to couple noise between devices and reduce timing margins. The use of fan out devices keeps clocks paths isolated and guards against these problems
Figure 3a. Board Level Timing: Star Wired Timing Distribution.
Figure 3b. Board Level Timing: Controlled Timing Distribution.
For OEM designers, system timing is a development dilemma. While synchronization and clock driver issues impose mandatory system design constraints, system timing does not provide any differentiation at the product level. Still, timing requirements are more important than ever, with increasing throughputs and the convergence of time division multiplex (TDM) services on packet- and cell-switched networks.
Figure 4. Clock Switching Examples.
Like many issues in electronics today, these challenges are being addressed by third party chip designers who are producing integrated timing solutions. By using these integrated timing solutions, OEM customers can focus on other areas where they add differentiation and value. Such products handle a variety of clock synthesis, synchronization and driver issues while cutting development time and saving on board real estate.
Scalability and flexibility enable the designer to use a single silicon solution for various product configurations, thereby leveraging their engineering investments. Some silicon solutions available today can scale from small single board systems with a simple timing architecture and simple input signal, to large systems where timing needs to be distributed to multiple multi-line-card shelves with multiple levels of redundancy. Standard product communications chips need to be able to support various input clock frequencies and generate output signals compatible with a variety of reference clock requirements for Pleisiochronous Digital Hierarchy (PDH), SONET (Synchronous Optical Network)/SDH (Synchronous Digital Hierarchy) and in some cases, even data services, such as Ethernet and Fibre Channel. The addition of programmable frequency outputs gives board designers more flexibility for their designs.
Driver power refers to the ability of any clock chip to propel a signal across a distance. The key, of course, is to provide appropriate voltage levels while maintaining proper phase or avoiding skew, and matching the required impedance of the receiving circuit. Support for low voltage positive emitter coupled logic (LVPECL), low voltage differential signaling (LVDS), and complementary metal oxide semiconductor (CMOS) is important.
Standards compliance is needed by any device connecting to the public network. Synchronization standards impose strict timing, format, and signal definitions set by recognized standards organization including: International Telecommunication Union (ITU), American National Standards Institute (ANSI), and Telcordia.
As design engineers explore how system-timing needs are changing, they should look at new approaches and solutions. By focusing on integrated solutions, they can reduce their time-to-market while addressing their network and system synchronization needs. By doing so, designers can emphasize product differentiating features while keeping pace with the growing needs and demands of synchronization.