When you drop a battery-powered device, the impact can open internal contacts for as long as 10ms, producing a momentary loss of power that can cause a false low battery indication. You can insure continuity of power by adding a large capacitor across the battery, but the capacitor must provide a certain amount of voltage headroom as margin against the discharge of load current. The capacitor voltage varies with discharge current as dV = Idt/C, so insufficient headroom calls for capacitance.
Another problem is that large capacitors tend to be leaky. Capacitor leakage is usually not a problem during normal operation, but during "sleep mode" it can be a substantial fraction of the total quiescent current, and thereby represent a significant reduction in battery life. The circuit of Figure 1 solves all of these problems.
Figure 1: This circuit removes discontinuities in power by backing up the battery (two AA cells) with charge on a reserve capacitor.
Two AA batteries provide 3V power, which is boosted to 3.3V by a step up dc-dc converter (U3). The large reserve capacitor of 2mF or 4mF is charged from the 3.3V output via a SPST CMOS analog switch (U1). The output of this 175W switch charges the reserve capacitor and drives the input of a low-dropout linear regulator (U2). U2's output is set to provide 1.68V when the battery is removed. The output is also divided down by the 80k/120k divider to trip an internal comparator connected to the low-battery input (LBI). The comparator's open-drain output (LBO) feeds back to U1's digital input (DIN), which turns the switch on (high) and off (low).
Figures 2-5 show the circuit performance for different values of reserve capacitor and load current. Figures 5-6 remove switch-response time by wiring the switch in the ON position.
Figure 2: The circuit with 4mF reserve capacitor and 100uA load: after removing the battery, power remains for 8.7s.
Figure 3: The circuit with 4mF reserve capacitor and 100mA load: after removing the battery, power remains for 10.8ms.
Figure 4: The circuit with 2mF reserve capacitor and 100uA load: after removing the battery, power remains for 1.48s.
Figure 5: circuit with 2mF reserve capacitor and 100mA load: after removing the battery, power remains for 920uS.
Figure 6: circuit with 2mF reserve capacitor, 100uA load, and switch wired closed: after removing the battery, power remains for 544ms.
Figure 7: The circuit with 2mF reserve capacitor, 100mA load, and switch wired closed: after removing the battery, power remains for 1.08ms.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.