AUSTIN, Texas " Chip designers are wielding new weapons in the struggle to control power leakage. Transistors with more than one threshold voltage, chips with multiple voltage "islands" and substrate-biasing techniques are among the schemes being brought to bear to quell what an IBM manager called "clearly the most pressing problem facing our industry, one that threatens our very lifeblood."
Ultimately, the semiconductor industry will need to come up with "a game-changing" form of innovation, something as monumental as the switch from bipolar to CMOS, Mark Papermaster, vice president of technology development at IBM Corp.'s systems group, said last week at an IBM-organized conference here on energy-efficient design. But in the near term, engineers are falling back on a handful of important design tricks to reduce power consumption.
IBM's Power 5 server processor, coming to market soon, incorporates power-management techniques that, for example, turn off the on-chip memory controller when that function is not needed. Implementing this technique required "significant investments in verification" tools, Papermaster said.
System performance is enhanced with much larger cache arrays than usual, which tend to burn less power than digital logic. And simultaneous multithreading is used to feed both processing units on the Power 5.
The net effect is that the processor, which will be introduced at about 2 GHz on a 130-nanometer process and then move to 90 nm, will maintain the historical rate of improvements in transaction processing. But IBM expects the frequency enhancements over the Power 5's lifetime to be modest compared with previous processors, which enjoyed a doubling in frequency every 18 months or so, Papermaster said.
Raul Camposano, chief technology officer at Synopsys Inc., noted that of the $5.7 billion the electronic design automation industry garners in annual revenues, only about $50 million to $100 million comes from power-management tools. "[That] is not huge when one considers the magnitude of the problem," he said.
Still, Camposano said that EDA vendors are supporting several important techniques that could help reduce power. "As we scale down, the process variations are getting much larger, and we may need statistical timing to deal with this," he said (see Feb. 9, page 1).
The problems with leakage, combined with higher mask costs, are likely to have profound implications on the progression to new process technology nodes, he said. With leakage accounting for more half of all power at the 45-nm node, "All the nodes will coexist for longer periods," Camposano said. "For some applications, designers will go to the newer node, others will not, and these will be economic decisions."
Clock gating is being introduced rapidly, but requires careful power grid planning. Many companies are implementing chips with multiple threshold voltages, a movement that has been under way for several years in tandem with the development of low-power libraries, he said.
"Multi-Vt transistors on SOI [silicon-on-insulator] will buy us maybe 25 to 30 percent power savings. Ahead of us we have new gate oxide materials, multigate transistors, fully depleted SOI, raised source-drain structures. Those should take the industry to terahertz speeds," he said.
Camposano cited several research projects with Synopsys customers to implement multi-Vt transistors. One chip company tested 180-nm circuits and found that implementing both high- and low-Vt transistors resulted in a fourfold improvement in leakage, while switching speeds went from 28 picoseconds for the low-Vt transistors to 36 ps for the high-Vt 180-nm devices. However, at 130 nm the results were much different. Leakage fell sharply, but at a higher cost: a 60 percent degradation in switching speeds for the higher-Vt 130-nm transistors.
In a speech at the IBM conference, Camposano noted that ARM Ltd. has introduced an adaptive power controller on one of its processor cores. Elsewhere, Philips Semiconductors created a power-saving asynchronous 8051 core design for a smart-card application, and National Semiconductor Corp.'s adaptive voltage- and frequency-scaling techniques appear promising, he said.
With multi-Vt designs enjoying broad support, a major effort is under way to develop tools and libraries to support the design of chips with multiple operating voltages, said Robert Johnson, director of strategic marketing at the Austin-based silicon correlation division of Magma Design Automation Inc. (formerly Silicon Metrics Inc.).
Already, companies in the wireless communications industry are implementing voltage islands, which allow entire blocks to use the minimum supply voltage needed to achieve timing. The technique requires care in the design of power distribution, including "electrical fencing" to prevent an indeterminate state in a powered-down block from corrupting an active block.
Working with multiple voltage islands requires EDA tools that support timing and power analysis across multiple voltage domains simultaneously. Automated signal-level checking is needed to avoid problems as signals drive between voltage domains. And voltage islands require more sophisticated floor-planning and placement tools, said Johnson.
"Some people have found ways to use the existing tools for multivoltage designs," Johnson said, adding that libraries and design tools are "starting to support multivoltage design techniques."
Designing with multiple voltages is driving the industry toward more complex cell models, said Louis Scheffer, a research fellow at Cadence Design Systems Inc. He pointed to the scalable polynomial-delay models from Synopsys as well as to Cadence's effective current source model (ECSM) as examples.
"To reduce power, designers are going to multiple power supplies, and so we need to compute accurate delays under a wide variety of supply voltages. The old standard, the .lib model, had only linear effects of voltage on delay, which is definitely not good enough," Scheffer said.
Cadence's ECSM approach is based on storing the I-V (current-voltage) characteristics of the outputs. Compared with just monitoring delays, the I-V-based models vary in a more predictable way as the supply voltage is changed, Scheffer said. "As a bonus, it also lets you calculate other electrical effects such as noise [in particular crosstalk] accurately, which a pure delay model does not."
Johnson said Magma late this year will introduce a new version of its cell characterization tool, called the SiliconSmart Cell Rater, which supports both timing and power analysis. That will make it possible for all the major vendors to create models that better support multivoltage design techniques, he said.
"Power is where we've put the bulk of our efforts in the last year," Johnson said. "When we go out to talk to customers, we find that while controlling noise is the sizzle, power is the steak, the challenge they are really concerned about."
Back-bias techniques, in which a transistor's substrate bias is adjusted, are another key method of controlling power. Normally in digital logic, the substrate in an NMOS transistor is tied to ground, while the substrate in the PMOS transistor is tied to Vdd. As a negative-bias voltage is applied, creating what is called a reverse bulk bias, the threshold voltage increases and leakage current is reduced, Johnson said. When performance is needed, a forward bulk bias is created, causing leakage current to increase.
Intel Corp. has used biasing techniques in its Pentium 4 processors to achieve a better speed bin--that is, a bigger percentage of higher-frequency chips that are within the acceptable power envelope. Texas Instruments Inc. also is working with back-bias techniques for its low-power transistors.
Michael Rosenfield, director of IBM's Austin research laboratory, said IBM has no immediate plans to introduce back-bias techniques for its high-performance processors, such as the Power series. Such techniques could be employed for the low-power embedded processors, he added.