New single-IF heterodyne receiver schemes, as well as sophisticated power amplifier linearization algorithms, are imposing challenging requirements for high-IF handling capability on analog-to-digital converter (ADC) performance. These factors, along with the perspective of integrating RF front-end and IF ADC rather than integrating the ADC itself with a digital downconverter (DDC), are pushing the converter's inherent jitter performance well below half a picosecond.
In fact, the main limitation to the resolution of each of these systems remains the ADC's signal-to-noise ratio (SNR). But the SNR of 12+ bit converters is in turn limited by jitter when the IF of the receiver is pushed any higher than 70 MHz. This leads to the need for a reliable, direct way to assess ADC jitter values.
In this two-part series, we'll detail a way to measure sub-picosecond jitter performance in an A/D design. In part 1, we'll look at ways to extract the cycle jitter as well as ways to remove dynamic effects and nonlinearities. We'll also look at data capture and extraction issues. Then in Part 2, we'll further the discussion by exploring the impact of jitter on SNR plots as well as the use of the sub-picosecond measurement technique for the development of a 14-bit ADC test chip.
Estimating Aperture Uncertainty
The timing uncertainty affecting the sampling instant of the sample/hold front-end needed in such ADCs is given by the root-mean-square (rms) combination of external clock synchronization source and on-chip clock pre-amplification, conditioning and distribution network. Several methods have been proposed in order to estimate the aperture uncertainty of sampling circuits. The simplest and most widely adopted method1 infers the jitter value indirectly from the SNR measurements taken at high input frequency, where the random deviation T of the occurrence of the sampling edge translates into a random voltage error σVjitter that dominates the noise deviation σV. Retro-fitting is usually accomplished by means of the formula shown in Equation 1 and applied to a sinusoidal input of amplitude AIN and angular frequency ωIN(ωIN=2ƒIN), written as VIN(t) = AIN-sin(ωINt):
Imperfect knowledge of the true values of thermal noise, random non-linearity contributions2, and any additional noise effects in Equation 1 requires expert guesswork to determine the lowest value of ƒIN for which the formula can be effectively applied. Skipping the math and forcing the ƒIN to extremely high frequencies "just to err on the safe side" can exacerbate a host of jitter-unrelated noise terms into the SNR, which could end up masking the wanted jitter term itself.
Moreover, the statistic nature of the phenomenon leads to different readings of the SNR at high IF acquired at different instants, even for data arrays of 16,000 or more, and the definition of the "true" SNR is somewhat arbitrary unless Allan variance or similar math tools are used. Lastly, good clock sources at high frequency are not easy to find.
Using the following method, a designer can first identify and then minimize the jitter contributed from external instrumentation, leading to the optimization of the total source plus on-chip clock aperture uncertainty in the design of critical sampling circuits. One successful example is an experimental 14-b, 65-MSample/s switched-capacitor pipeline ADC designed to target the specifications of base stations for 3G wireless standards, requiring IF sampling capability of 70 to 220 MHz. The ADC shows a period jitter as low as 250 fs, the best figures proven to date for CMOS-based clocks, enabling excellent SNR values of 69.3 dBFS at 65 MSamples/s, 220 MHz IF. In addition, a 14-bit, 125-MSample/s ADC has been developed that features 260-fs period jitter at 220MHz. The circuits have been designed in SiGe BiCMOS and CMOS technologies respectively.
Extracting Cycle Jitter
Although so-called coherent sampling techniques, whereby a fixed time delay coherence was set between input waveform and sampling clock, have been successfully employed in the past2-4, a more robust implementation of the idea relies on the parametric analysis of the correlation between the instantaneous voltage jitter observed and the phase of the input when such a noise is measured. In practice, the method first verifies that the measured noise dependency on the phase of the input sinusoid actually follows the theoretical expectation for jitter. This takes the guesswork out of the application of formulas like Equation 1.
The shape of the jitter vs. input waveform's phase can be verified against the theory and prove the suitability of the collected data for reliable jitter estimation. Once the collected data match the expected profile, the jitter estimation can be treated as the numerical solution of a multivariate least mean squares (LMS) problem: fitting the amplitude of the theoretical curves to those obtained after characterization.
As intuition suggests, the theoretical rms voltage error σVjitter induced by the clock cycle jitter (defined as the standard deviation of the Gaussian distribution of the periods, σT) is directly proportional to the slope of the input waveform under sampling, as expressed by the well-known Equation 2:
Equation 2 expresses in mathematical terms the obvious concept that little or no error is induced by a jittery sampling instant on the sampled value of an input sinusoid when observed at its peak. When the input is close to the zero crossing instead, an error in the sampling time induces substantial deviation of the sampled voltage from the ideal value, since the rate of variation of the signal with time is so fast. The formula would suggest that quantifying jitter is just a matter of picking the zero crossing of the input signal: there's of course much more to it.
Removing Dynamic Effects, Non-Linearities
The main issue to be solved when trying to determine the jitter associated with the sampling process of an ADC is the removal of both dynamic effects and non-linearities, which are notoriously difficult to identify and treat. In order to isolate the random contribution of the jitter stochastic process, the best possible condition is to feed the quantizer section of the ADC with a static input: dc. From an operational standpoint, since high-speed ADCs are normally fed through a transformer at the input, this can be accomplished via a coherent sampling of the input; i.e., adopting a sampling rate ƒs=ƒIN/N (N integer) to sample the same point in every period, or every few periods, as shown in Figure 1.
Figure 1: Example of coherent sampling. In this diagram, the fast input sinusoid is sampled once every 6 periods, and always at the same instant, to give a dc waveform (dashed line) after the sample/hold.
A good quality sinusoidal signal source allows the phase of its output to be varied in continuous fashion, or at least in small steps. The sampling instant can be set to occur always at the VIN peak (90 deg. phase of the input waveform), always at the zero crossing (0 deg. phase), or at any intermediate point of the waveform, when the sampling clock and the input source are locked to the same quartz reference with phase-locked loops (PLLs). After the sample/hold the signal to be quantized is indeed a dc, positioned at different levels depending on the acquisition phase, as shown in Figure 1. This mimics the classic idle-input noise test reported in Figure 2, where the differential VIN is set to 0 V and, as a consequence, the output code lies in the middle of the digital range (with a certain offset).
Figure 2: Idle-test Gaussian noise distribution yielded by the ADC under test.
Therefore, the Gaussian noise distribution featured around each digital code can be measured. Figure 2 represents the experimental outcome of the procedure used to collect the code histograms, which is repeated at every dc level by tuning the phase of the input vs. the occurrence of the sampling clock edges. If jitter affects the aperture instant, the Gaussian curve will be wider. In agreement with Equation 2, samples taken close to the zero-crossings will show wider distributions (high signal slope), whereas the variance will be narrower for samples collected near the sinusoid peaks.
In this latter case, the standard deviation of the Gaussian noise actually represents the ADC's thermal noise floor, plus injection from the circuit substrate, and any possible term that is not related to jitter. Adopting "locked histogram" methods3-6 causes many dynamic non-idealities hidden in the quantizer, such as reference bounce, hysteresis effects in the stages, and more, to be completely eliminated. So these methods present clear advantages over alternative techniques such as time-beat2 where the samples still change with time during the measurement.
Data Capture and Jitter Extraction
To exemplify the jitter assessment procedure in a practical way, let's go through the testing procedure adopted to characterize a concept high-speed 14-bit ADC designed for a single-IF receiver architecture used in a 3G wireless base transceiver station (BTS). In order to expunge any other high-frequency effect, initially a sampling rate ƒs = 30 MSamples/s was chosen. Jitter as introduced by the on-chip clock circuitry is"to a first order"independent of the clock speed, and the aperture uncertainty assessment made at 30 MHz can be used at 65 or 80 MHz virtually without corrections.
The input sinusoid was accordingly run at multiples of ƒs or N x 30MHz, keeping -1-dBFS amplitude. The input amplitude does not enter the SNR expression (see Equation 1) but does impact the voltage noise generated by a given time jitter, hence amplitudes in excess of 1 Vp-p are useful to lift the jitter signature above the other contributions.
The phase relationship Δφ between the input waveform and the sampling clock can be easily regulated via the phase-frequency detector (PFD) of the PLLs used to lock analog input and clock generators to a common reference to obtain coherence, as suggested in Figure 1. This option is usually built-in with the instrumentation, and does not require any external components. Alternatively, the clock controlling the sampling front can be obtained by squaring the input signal through a comparator, with the phase skew " regulated with a tunable delay line. However, such a solution introduces additional uncertainty, and does not allow for the flexibility of the input being a multiple of the clock, which greatly improves the resolution of the technique as will be shown in the following.
The data collected at different relative phases Δφ of the input signal vs. clock are represented in Figure 3. The statistical confidence of the data as collected on every σV measured is based on a series of 4096 observations for each point of the curves. If the analysis is limited to a series of a few hundred observations, the random nature of the jitter disperses the experimental curves into scattered collections of points and the data fitting becomes even more complicated. Accordingly, the tidiness of the plots collected in the lab and shown in Figure 3 increases with higher values of noise, since the data's uncertainty/average ratio becomes more favorable.
Figure 3: Total σV vs number of δψ steps taken at 30-MSample/s clock rate, and respectively a) 30MHz, b) 90MHz, and c) 150MHz coherent input.
Whereas a tight determination of the relative phase " is easy enough, it is virtually impossible to control the absolute value of the phase of the input, needed to calculate the jitter expected after Equation 2. The three plots in Figure 3 are a demonstration of this, as each starts with a random phase. The phase needed could be extracted in one of the following ways:
- from the collection of the mean of the Gaussian distributions of the noise; that is, from the center code measured at the ADC output. But as shown in Figure 2, any offset of the ADC along with any shape distortion on the input introduces phase skewing.
- more accurately, from the fitting of the data to the theoretical noise vs. phase dependency (which is a pulsed cosine, per Equation 2.
The second method has the additional advantage of permitting the designer to infer the RMS jitter from the same best-fit function found by the LMS search. All the dashed curves drawn in Figure 3 can be obtained by following this approach. The LabView integrated environment for laboratory testing features a built-in best-fit function adopting a multivariate Levenberg-Marquardt algorithm and has been used in Figure 3. Data post-processing can be implemented in other software suites, such as Matlab, but data porting is needed and the procedure is less convenient.
A very simple LabView code can fit virtually every distribution collected: the LMS algorithm's flexibility permits optimizing the data's baseline (which equals the noise floor level), the pulsed cosine amplitude (which equals the clock jitter contribution), and the starting phase of the experimental curve (which equals the absolute phase generated by the source). The adherence of the experimental data to the sought theoretical behavior across the whole 360-deg. phase range in Figure 3a provides significantly better confidence than the traditional re-ordering of the measured points.2
To extract the cycle jitter from the fitted co-sinusoid amplitude, it is now sufficient to invert Equation 2 written for the full amplitude, i.e. where cos(ωINt) = 1. By taking into account that 1 least significant bit (LSB) of a 14-bit ADC operated at a 2-Vp-p input range equals 122 μV, and that the input sinusoid is kept at -1 dBFS (i.e. AIN is approximately 891mV) to avoid clipping, the jitter value extracted from the best fit of 2.08 LSB noise detected at 30MHz input using Equation 1 is as high as σT = 1.51 ps.
The technique applied to the case depicted in Fig. 3a provides evidence of a sizable jitter problem in the clock source/board/ADC chip system, which will surely hamper the SNR at high IF sampling.
The operating principle of the method still works for the case of undersampled inputs, yielding even stronger evidence. Figure 3a showed the best fit obtained for ƒIN=ƒs, where the peak voltage noise induced by jitter only amounts to about 2.4 LSBs. Owing to the great flexibility of the technique, ƒIN was raised to 90 MHz, picking one sample every three input periods. The curve matching this new data is reported in Fig. 3b, and shows even higher adherence between prediction and measurement. As expected, the jitter prediction does not change substantially, yet it becomes more precise: the 5.86 LSB measured at 90 MHz give σT = 1.42 ps.
A final test extends the principle even further by running the ADC at higher frequency input (150 MHz, or 1 sample taken out of 5 input periods). The voltage noise increases linearly with the IF fed to the converter, per Equation 1, enhancing the cleanliness of the experimental curve and consequently providing for the best confidence in the jitter extraction. The last correlation is illustrated in Figure 3c, and yields 9.91 LSB at 150MHz, which are fitted by σT = 1.44 ps. The estimate is almost identical to the 90 MHz estimation, which underlines the better precision gained by running the tests at higher ƒIN.
The slight discrepancy shown by each plot near the narrow minimum is also readily rationalized: when the jitter impact is zeroed at the top and bottom of the sinusoidal input, the total noise probed is limited by the thermal floor term, hence the cusp point predicted by Equation 2 can never be seen. The limitation at the bottom is around 1.25LSB, consistent with the idle-input test run on the same ADC and shown in Figure 2.
The formula itself could be improved by adding a constant baseline to the SNR (the traditional "water-filling" term). But in reality the jitter estimate is hardly impacted by this mathematical accident, since forcing the Levenberg-Marquardt algorithm to fit the experimental minimum or not just causes differences of a few femtoseconds. In fact, the difference between the maxima and minima of the voltage noise represented in Figure 3 are to be calculated in rms terms, and as such any inaccuracy in the lower part of the plots weighs significantly less than an error in the top of the curve. However, this also causes any high jitter "spikes" often observed during this kind of characterization to completely falsify the jitter estimate achieved through the technique, if only zero-crossing and input peak were used.
The almost perfect consistency of the jitter values as derived at different input frequency, as opposed to the dependency versus phase, deserves additional remarks. After Equation 1 σVjitter is directly proportional to ƒIN (for constant σT). The data shown in Figure 3 demonstrates that the excess noise scales up almost linearly with input frequency. Additional effects such as noise modulation due to the uneven code bins distribution, quantified by differential non-linearity (DNL) do not scale with fIN, and have been consequently isolated. This constitutes a distinctive advantage of the technique over other approaches.
That wraps up Part 1 in our series on measuring sub-picosecond jitter performance. In Part 2, we'll further the discussion by exploring the impact of jitter on SNR plots as well as the impact of the sub-picosecond measurement technique on the development of a 14-bit ADC test chip.
M. Shinagawa, Y. Akazawa, and T. Wakimoto, "Jitter analysis of high-speed sampling systems", IEEE Journal of Solid-State Circuits, vol. 25, no. 1, Feb. 1990, pp. 220-224.
Y. Langard, J.-L. Balat, and J. Durand, "An improved method of ADC jitter measurement", in Proceedings of the IEEE ITC, Washington, DC, 1994, pp. 763-770.
G. Chiorboli, M. Fontanili, and C. Morandi, "A new method for estimating the aperture uncertainty of A/D converters", in Proceedings of the IEEE IMTC, Ottawa, Canada, 1997, pp. 632-635.
T. Kuyel, "Method and System For Measuring Jitter ", U.S. Patent 6,640,193.
M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal Circuits. IEEE Computer Society Press, Piscataway, NJ, 1987.
A Zanchi, I. Papantonopoulos, and F. Tsay, "Measurement and Spice prediction of sub-picosecond clock jitter in A/D converters", in Proceedings of ISCAS 2003, May 2003, Bangkok (Thailand), vol. 5, pp. 557-560.
A. Loloee, A. Zanchi, H. Jin, S. Shehata, and E. Bartolome, "A 12b 80MSps pipeline ADC core with 190mW consumption from 3V in 0.18μm digital CMOS", in Proceedings of ESSCIRC 2002, pp. 467-470, Florence (Italy), Sep. 2002.
A. Zanchi, A. Bonfanti, S. Levantino, and C. Samori, "General SSCR vs. cycle-to-cycle jitter relationship with application to the phase noise in PLL", in Proceedings of the IEEE SSMSD, Austin, TX, 2001, pp. 32-37.
About the authors
Alfio Zanchi is a mixed-signal design engineer working on high-speed ADCs with the Wireless Infrastructure business unit of Texas Instruments, Dallas, TX. He holds a PhD degree in Electronics and Communications Engineering from the Politecnico di Milano, Italy. Alfio can be reached at email@example.com.
Ioannis Papantonopoulos is a test and systems engineer working on data converter and RF products in Texas Instruments' Wireless Infrastructure business unit, Dallas, TX. He received his BSEE and MSEE degrees from the University of Maine at Orono, and an MBA degree from Southern Methodist University, Dallas, TX. He can be reached at firstname.lastname@example.org.